Timing model for VCORE

6 files changed, 152 insertions, 17 deletions

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 7fe5d82..781509f 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -78,6 +78,7 @@ enum uarch_op_t {
    ALU_OP=1,
    SFU_OP,
    TENSOR_CORE_OP,
+   VP_CORE_OP,
    ALU_SFU_OP,
    LOAD_OP,
    STORE_OP,
@@ -135,6 +136,7 @@ enum operation_pipeline_t {
     SP__OP,
     SFU__OP,
     TENSOR_CORE__OP,
+    VP_CORE__OP,
     MEM__OP
 };
 typedef enum operation_pipeline_t operation_pipeline;
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 2fe5667..1ad12ee 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -542,7 +542,7 @@ void ptx_instruction::set_mul_div_or_other_archop(){
 				    sp_op=INT_DIV_OP;
 				break;
 				default:
-					if((op==ALU_OP)||(op==TENSOR_CORE_OP))
+					if((op==ALU_OP)||(op==VP_CORE_OP))
 					    sp_op=INT__OP;
 					break;
 			}
@@ -649,9 +649,11 @@ void ptx_instruction::set_opcode_and_latency()
        break;
    case LD_OP: op = LOAD_OP; break;
    case MMA_LD_OP: op = LOAD_OP; break;
+   case VP_LD_OP: op = LOAD_OP; break;
    case LDU_OP: op = LOAD_OP; break;
    case ST_OP: op = STORE_OP; break;
    case MMA_ST_OP: op = STORE_OP; break;
+   case VP_ST_OP: op = STORE_OP; break;
    case BRA_OP: op = BRANCH_OP; break;
    case BREAKADDR_OP: op = BRANCH_OP; break;
    case TEX_OP: op = LOAD_OP; mem_op=TEX; break;
@@ -799,6 +801,26 @@ void ptx_instruction::set_opcode_and_latency()
 	   initiation_interval = 64;
            op=TENSOR_CORE_OP;
 	   break;
+   case VP_MMA_OP:
+	   if(get_wmma_type()==VP_MMA4)
+           {
+	   latency = 5;
+	   initiation_interval = 5;
+           }
+	   if(get_wmma_type()==VP_MMA8)
+           {
+	   latency = 5;
+	   initiation_interval = 5;
+           }
+	   if(get_wmma_type()==VP_MMA16)
+           {
+	   latency = 5;
+	   initiation_interval = 5;
+           }
+           op=VP_CORE_OP;
+           op=VP_CORE_OP;
+           op=VP_CORE_OP;
+	   break;
    case SHFL_OP:
 	   latency = 32;
 	   initiation_interval = 15;
@@ -900,10 +922,10 @@ void ptx_instruction::pre_decode()
    case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break;
    default: 
       //if( m_opcode == LD_OP || m_opcode == LDU_OP ) 
-      if(  m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) 
+      if( m_opcode ==VP_LD_OP || m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) 
          cache_op = CACHE_ALL;
       //else if( m_opcode == ST_OP ) 
-      else if( m_opcode == ST_OP || m_opcode == ST_OP ) 
+      else if( m_opcode == VP_ST_OP ||m_opcode == MMA_ST_OP || m_opcode == ST_OP ) 
          cache_op = CACHE_WRITE_BACK;
       else if( m_opcode == ATOM_OP ) 
          cache_op = CACHE_GLOBAL;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index cb4556e..e025013 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1093,7 +1093,7 @@ public:
    int membar_level() const { return m_membar_level; }
 
    bool has_memory_read() const {
-      if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP) 
+      if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP || m_opcode==VP_LD_OP) 
          return true;
       // Check PTXPlus operand type below
       // Source operands are memory operands
@@ -1105,7 +1105,7 @@ public:
       return false;
    }
    bool has_memory_write() const {
-      if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true;
+      if( m_opcode == ST_OP || m_opcode==MMA_ST_OP || m_opcode==VP_ST_OP ) return true;
       // Check PTXPlus operand type below
       // Destination operand is a memory operand
       ptx_instruction::const_iterator op=op_iter_begin();
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 3e064c7..7a797b5 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -309,6 +309,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core,
                 "number of collector units (default = 4)", 
                 "4");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_units_vp_core", OPT_INT32, &gpgpu_operand_collector_num_units_vp_core,
+                "number of collector units (default = 4)", 
+                "4");
     option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem", OPT_INT32, &gpgpu_operand_collector_num_units_mem,
                 "number of collector units (default = 2)", 
                 "2");
@@ -324,6 +327,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_vp_core,
+                           "number of collector unit in ports (default = 1)", 
+                           "1");
     option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -339,6 +345,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core,
                            "number of collector unit in ports (default = 1)", 
                            "1");
+    option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_vp_core,
+                           "number of collector unit in ports (default = 1)", 
+                           "1");
     option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem,
                            "number of collector unit in ports (default = 1)", 
                            "1");
@@ -359,8 +368,8 @@ void shader_core_config::reg_options(class OptionParser * opp)
                             "1");
     option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
                             "Pipeline widths "
-                            "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
-                            "1,1,1,1,1,1,1,1,1" );
+                            "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_VP_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
+                            "1,1,1,1,1,1,1,1,1,1,1" );
     option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units,
                             "Number of SP units (default=1)",
                             "1");
@@ -370,6 +379,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units,
                             "Number of tensor_core units (default=1)",
                             "1");
+    option_parser_register(opp, "-gpgpu_num_vp_core_units", OPT_INT32, &gpgpu_num_vp_core_units,
+                            "Number of vp_core units (default=1)",
+                            "1");
     option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
                             "Number if ldst units (default=1) WARNING: not hooked up to anything",
                              "1");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 226e7f0..6f11ad9 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -149,6 +149,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
+                                       &m_pipeline_reg[ID_OC_VP_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
                                      )
@@ -164,6 +165,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                                     &m_pipeline_reg[ID_OC_SP],
                                                     &m_pipeline_reg[ID_OC_SFU],
                                                     &m_pipeline_reg[ID_OC_TENSOR_CORE],
+                                                    &m_pipeline_reg[ID_OC_VP_CORE],
                                                     &m_pipeline_reg[ID_OC_MEM],
                                                     i,
                                                     config->gpgpu_scheduler_string
@@ -180,6 +182,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
+                                       &m_pipeline_reg[ID_OC_VP_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i
                                      )
@@ -195,6 +198,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
                                        &m_pipeline_reg[ID_OC_SP],
                                        &m_pipeline_reg[ID_OC_SFU],
                                        &m_pipeline_reg[ID_OC_TENSOR_CORE],
+                                       &m_pipeline_reg[ID_OC_VP_CORE],
                                        &m_pipeline_reg[ID_OC_MEM],
                                        i,
                                        config->gpgpu_scheduler_string
@@ -215,10 +219,11 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     }
     
     //op collector configuration
-    enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS, GEN_CUS };
+    enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, VP_CORE_CUS, MEM_CUS, GEN_CUS };
     m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
     m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
     m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core);
+    m_operand_collector.add_cu_set(VP_CORE_CUS, config->gpgpu_operand_collector_num_units_vp_core, config->gpgpu_operand_collector_num_out_ports_vp_core);
     m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
     m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
     
@@ -252,6 +257,14 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         in_ports.clear(),out_ports.clear(),cu_sets.clear();
     }
     
+    for (unsigned i = 0; i < config->gpgpu_operand_collector_num_in_ports_vp_core; i++) {
+        in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]);
+        out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]);
+        cu_sets.push_back((unsigned)VP_CORE_CUS);
+        cu_sets.push_back((unsigned)GEN_CUS);
+        m_operand_collector.add_port(in_ports,out_ports,cu_sets);
+        in_ports.clear(),out_ports.clear(),cu_sets.clear();
+    }
 
     for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
         in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
@@ -267,10 +280,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
+        in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]);
         in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
+        out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]);
         out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
         cu_sets.push_back((unsigned)GEN_CUS);   
         m_operand_collector.add_port(in_ports,out_ports,cu_sets);
@@ -280,7 +295,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
     m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
     
     // execute
-    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
+    m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + config->gpgpu_num_vp_core_units + 1; // sp_unit, sfu, ldst_unit
     //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
     
@@ -304,6 +319,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
         m_issue_port.push_back(OC_EX_TENSOR_CORE);
     }
     
+    for (int k = 0; k < config->gpgpu_num_vp_core_units; k++) {
+        m_fu.push_back(new vp_core( &m_pipeline_reg[EX_WB], m_config, this ));
+        m_dispatch_port.push_back(ID_OC_VP_CORE);
+        m_issue_port.push_back(OC_EX_VP_CORE);
+    }
+    
     m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id );
     m_fu.push_back(m_ldst_unit);
     m_dispatch_port.push_back(ID_OC_MEM);
@@ -910,7 +931,8 @@ void scheduler_unit::cycle()
                             bool sp_pipe_avail = m_sp_out->has_free();
                             bool sfu_pipe_avail = m_sfu_out->has_free();
                             bool tensor_core_pipe_avail = m_tensor_core_out->has_free();
-                            if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP)) {
+                            bool vp_core_pipe_avail = m_vp_core_out->has_free();
+                            if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) && (pI->op !=VP_CORE_OP)) {
                                 
                                 //Jin: special for CDP api
                                 if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
@@ -950,6 +972,14 @@ void scheduler_unit::cycle()
                                     issued_inst=true;
                                     warp_inst_issued = true;
                                 }
+				}
+                             else if ( (pI->op == VP_CORE_OP) ) {
+                                if( vp_core_pipe_avail ) {
+                                    m_shader->issue_warp(*m_vp_core_out,pI,active_mask,warp_id);
+                                    issued++;
+                                    issued_inst=true;
+                                    warp_inst_issued = true;
+                                }
                             }                         }
                     } else {
                         SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n",
@@ -1116,10 +1146,11 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
                                register_set* sp_out,
                                register_set* sfu_out,
                                register_set* tensor_core_out,
+                               register_set* vp_core_out,
                                register_set* mem_out,
                                int id,
                                char* config_string )
-    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id )
+    : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id )
 {
     unsigned m_prioritization_readin;
     int ret = sscanf( config_string,
@@ -1548,6 +1579,12 @@ tensor_core:: tensor_core(  register_set* result_port, const shader_core_config
     m_name = "TENSOR_CORE"; 
 }
 
+vp_core:: vp_core(  register_set* result_port, const shader_core_config *config,shader_core_ctx *core  )
+    : pipelined_simd_unit(result_port,config,config->max_vp_core_latency,core)
+{ 
+    m_name = "VP_CORE"; 
+}
+
 
 void sfu::issue( register_set& source_reg )
 {
@@ -1569,6 +1606,16 @@ void tensor_core::issue( register_set& source_reg )
 	pipelined_simd_unit::issue(source_reg);
 }
 
+void vp_core::issue( register_set& source_reg )
+{
+    warp_inst_t** ready_reg = source_reg.get_ready();
+	//m_core->incexecstat((*ready_reg));
+
+	(*ready_reg)->op_pipe= VP_CORE__OP;
+	m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
+	pipelined_simd_unit::issue(source_reg);
+}
+
 
 void ldst_unit::active_lanes_in_pipeline(){
 	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
@@ -1599,6 +1646,13 @@ void tensor_core::active_lanes_in_pipeline(){
 	m_core->incfumemactivelanes_stat(active_count);
 }
 
+void vp_core::active_lanes_in_pipeline(){
+	unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
+	assert(active_count<=m_core->get_config()->warp_size);
+	m_core->incsfuactivelanes_stat(active_count);
+	m_core->incfuactivelanes_stat(active_count);
+	m_core->incfumemactivelanes_stat(active_count);
+}
 
 sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
     : pipelined_simd_unit(result_port,config,config->max_sp_latency,core)
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 90a3134..d292d56 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -319,11 +319,12 @@ public:
                    register_set* sp_out,
                    register_set* sfu_out,
                    register_set* tensor_core_out,
+                   register_set* vp_core_out,
                    register_set* mem_out,
                    int id) 
         : m_supervised_warps(), m_stats(stats), m_shader(shader),
         m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
-        m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
+        m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_vp_core_out(vp_core_out),m_mem_out(mem_out), m_id(id){}
     virtual ~scheduler_unit(){}
     virtual void add_supervised_warp_id(int i) {
         m_supervised_warps.push_back(&warp(i));
@@ -397,6 +398,7 @@ protected:
     register_set* m_sp_out;
     register_set* m_sfu_out;
     register_set* m_tensor_core_out;
+    register_set* m_vp_core_out;
     register_set* m_mem_out;
 
     int m_id;
@@ -410,9 +412,10 @@ public:
                     register_set* sp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
+                    register_set* vp_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ){}
 	virtual ~lrr_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -428,9 +431,10 @@ public:
                     register_set* sp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
+                    register_set* vp_core_out,
                     register_set* mem_out,
                     int id )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,vp_core_out, mem_out, id ){}
 	virtual ~gto_scheduler () {}
 	virtual void order_warps ();
     virtual void done_adding_supervised_warps() {
@@ -448,10 +452,11 @@ public:
                           register_set* sp_out,
                           register_set* sfu_out,
                           register_set* tensor_core_out,
+                          register_set* vp_core_out,
                           register_set* mem_out,
                           int id,
                           char* config_str )
-	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ),
+	: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ),
 	  m_pending_warps() 
     {
         unsigned inner_level_readin;
@@ -499,6 +504,7 @@ public:
                     register_set* sp_out,
                     register_set* sfu_out,
                     register_set* tensor_core_out,
+                    register_set* vp_core_out,
                     register_set* mem_out,
                     int id,
                     char* config_string );
@@ -1083,6 +1089,22 @@ public:
     virtual void active_lanes_in_pipeline();
     virtual void issue(  register_set& source_reg );
 };
+class vp_core : public pipelined_simd_unit
+{
+public:
+    vp_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
+    virtual bool can_issue( const warp_inst_t &inst ) const
+    {
+        switch(inst.op) {
+        case VP_CORE_OP: break;
+        default: return false;
+        }
+        return pipelined_simd_unit::can_issue(inst);
+    }
+    virtual void active_lanes_in_pipeline();
+    virtual void issue(  register_set& source_reg );
+};
+
 
 
 class sp_unit : public pipelined_simd_unit
@@ -1225,10 +1247,12 @@ enum pipeline_stage_name_t {
     ID_OC_SP=0,
     ID_OC_SFU,  
     ID_OC_TENSOR_CORE,  
+    ID_OC_VP_CORE,  
     ID_OC_MEM,  
     OC_EX_SP,
     OC_EX_SFU,
     OC_EX_TENSOR_CORE,
+    OC_EX_VP_CORE,
     OC_EX_MEM,
     EX_WB,
     N_PIPELINE_STAGES 
@@ -1238,10 +1262,12 @@ const char* const pipeline_stage_name_decode[] = {
     "ID_OC_SP",
     "ID_OC_SFU",  
     "ID_OC_TENSOR_CORE",  
+    "ID_OC_VP_CORE",  
     "ID_OC_MEM",  
     "OC_EX_SP",
     "OC_EX_SFU",
     "OC_EX_TENSOR_CORE",
+    "OC_EX_VP_CORE",
     "OC_EX_MEM",
     "EX_WB",
     "N_PIPELINE_STAGES" 
@@ -1286,13 +1312,21 @@ struct shader_core_config : public core_config
         max_warps_per_shader =  n_thread_per_shader/warp_size;
         assert( !(n_thread_per_shader % warp_size) );
         max_sfu_latency = 512;
-        max_tensor_core_latency = 64;
         max_sp_latency = 32;
+        
+	max_tensor_core_latency = 64;
         gpgpu_num_tensor_core_units=8;
         gpgpu_operand_collector_num_units_tensor_core=24;
         gpgpu_operand_collector_num_in_ports_tensor_core=8;
         gpgpu_operand_collector_num_out_ports_tensor_core=8;
-        m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
+        
+	max_vp_core_latency = 64;
+        gpgpu_num_vp_core_units=8;
+        gpgpu_operand_collector_num_units_vp_core=24;
+        gpgpu_operand_collector_num_in_ports_vp_core=8;
+        gpgpu_operand_collector_num_out_ports_vp_core=8;
+        
+	m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
         m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
         m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone);
         m_L1D_config.init(m_L1D_config.m_config_string,FuncCachePreferNone);
@@ -1339,24 +1373,28 @@ struct shader_core_config : public core_config
     int gpgpu_operand_collector_num_units_sp;
     int gpgpu_operand_collector_num_units_sfu;
     int gpgpu_operand_collector_num_units_tensor_core;
+    int gpgpu_operand_collector_num_units_vp_core;
     int gpgpu_operand_collector_num_units_mem;
     int gpgpu_operand_collector_num_units_gen;
 
     unsigned int gpgpu_operand_collector_num_in_ports_sp;
     unsigned int gpgpu_operand_collector_num_in_ports_sfu;
     unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
+    unsigned int gpgpu_operand_collector_num_in_ports_vp_core;
     unsigned int gpgpu_operand_collector_num_in_ports_mem;
     unsigned int gpgpu_operand_collector_num_in_ports_gen;
 
     unsigned int gpgpu_operand_collector_num_out_ports_sp;
     unsigned int gpgpu_operand_collector_num_out_ports_sfu;
     unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
+    unsigned int gpgpu_operand_collector_num_out_ports_vp_core;
     unsigned int gpgpu_operand_collector_num_out_ports_mem;
     unsigned int gpgpu_operand_collector_num_out_ports_gen;
 
     int gpgpu_num_sp_units;
     int gpgpu_num_sfu_units;
     int gpgpu_num_tensor_core_units;
+    int gpgpu_num_vp_core_units;
     int gpgpu_num_mem_units;
 
     //Shader core resources
@@ -1370,6 +1408,7 @@ struct shader_core_config : public core_config
     unsigned max_sp_latency;
     unsigned max_sfu_latency;
     unsigned max_tensor_core_latency;
+    unsigned max_vp_core_latency;
     
     unsigned n_simt_cores_per_cluster;
     unsigned n_simt_clusters;
@@ -1408,6 +1447,7 @@ struct shader_core_stats_pod {
     unsigned *m_num_sp_acesses;
     unsigned *m_num_sfu_acesses;
     unsigned *m_num_tensor_core_acesses;
+    unsigned *m_num_vp_core_acesses;
     unsigned *m_num_trans_acesses;
     unsigned *m_num_mem_acesses;
     unsigned *m_num_sp_committed;
@@ -1415,6 +1455,7 @@ struct shader_core_stats_pod {
     unsigned *m_num_tlb_accesses;
     unsigned *m_num_sfu_committed;
     unsigned *m_num_tensor_core_committed;
+    unsigned *m_num_vp_core_committed;
     unsigned *m_num_mem_committed;
     unsigned *m_read_regfile_acesses;
     unsigned *m_write_regfile_acesses;
@@ -1424,6 +1465,7 @@ struct shader_core_stats_pod {
     unsigned *m_active_sp_lanes;
     unsigned *m_active_sfu_lanes;
     unsigned *m_active_tensor_core_lanes;
+    unsigned *m_active_vp_core_lanes;
     unsigned *m_active_fu_lanes;
     unsigned *m_active_fu_mem_lanes;
     unsigned *m_n_diverge;    // number of divergence occurring in this shader
@@ -1496,6 +1538,7 @@ public:
         m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_num_vp_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
@@ -1504,10 +1547,12 @@ public:
         m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_active_vp_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
+        m_num_vp_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
         m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));