Fixing bug 59 + cleaning some code related to the power model

Review ID:32001

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]

4 files changed, 63 insertions, 91 deletions

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index d1acff6..f0966e6 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -82,14 +82,14 @@ enum uarch_op_t {
 };
 typedef enum uarch_op_t op_type;
 
-enum uarch_op2_t {
+enum uarch_operand_type_t {
 	UN_OP=-1,
     INT_OP,
     FP_OP
 };
-typedef enum uarch_op2_t op_type2;
+typedef enum uarch_operand_type_t types_of_operands;
 
-enum uarch_op3_t {
+enum special_operations_t {
     OTHER_OP,
     INT__OP,
 	INT_MUL24_OP,
@@ -99,24 +99,24 @@ enum uarch_op3_t {
     FP_MUL_OP,
     FP_DIV_OP,
     FP__OP,
-	 FP_SQRT_OP,
-	 FP_LG_OP,
-	 FP_SIN_OP,
-	 FP_EXP_OP
+	FP_SQRT_OP,
+	FP_LG_OP,
+	FP_SIN_OP,
+	FP_EXP_OP
 };
-typedef enum uarch_op3_t op_type3;
-enum uarch_op4_t {
+typedef enum special_operations_t special_ops; // Required to identify for the power model
+enum operation_pipeline_t {
     UNKOWN_OP,
     SP__OP,
     SFU__OP,
     MEM__OP
 };
-typedef enum uarch_op4_t op_type4;
-enum uarch_op5_t {
+typedef enum operation_pipeline_t operation_pipeline;
+enum mem_operation_t {
     NOT_TEX,
     TEX
 };
-typedef enum uarch_op5_t op_type5;
+typedef enum mem_operation_t mem_operation;
 
 enum _memory_op_t {
 	no_memory_op = 0,
@@ -679,10 +679,10 @@ public:
         pc=(address_type)-1;
         reconvergence_pc=(address_type)-1;
         op=NO_OP; 
-        op2=UN_OP;
-        op3=OTHER_OP;
-        op4=UNKOWN_OP;
-        op5=NOT_TEX;
+        oprnd_type=UN_OP;
+        sp_op=OTHER_OP;
+        op_pipe=UNKOWN_OP;
+        mem_op=NOT_TEX;
         num_operands=0;
         num_regs=0;
         memset(out, 0, sizeof(unsigned)); 
@@ -714,10 +714,10 @@ public:
     address_type pc;        // program counter address of instruction
     unsigned isize;         // size of instruction in bytes 
     op_type op;             // opcode (uarch visible)
-    op_type2 op2;           // opcode (uarch visible) determine if the operation is an interger or a floating point
-    op_type3 op3;           // opcode (uarch visible) determine if int_alu, fp_alu, int_mul ....
-    op_type4 op4;
-    op_type5 op5;
+    types_of_operands oprnd_type;     // code (uarch visible) identify if the operation is an interger or a floating point
+    special_ops sp_op;           // code (uarch visible) identify if int_alu, fp_alu, int_mul ....
+    operation_pipeline op_pipe;  // code (uarch visible) identify the pipeline of the operation (SP, SFU or MEM)
+    mem_operation mem_op;        // code (uarch visible) identify memory type
     _memory_op_t memory_op; // memory_op used by ptxplus 
     unsigned num_operands;
     unsigned num_regs; // count vector operand as one register operand
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 5c66c7a..a7294c1 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -467,52 +467,52 @@ std::string ptx_get_insn_str( address_type pc )
 }
 
 void ptx_instruction::set_fp_or_int_archop(){
-	op2=UN_OP;
+    oprnd_type=UN_OP;
 	if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){
 			// do nothing
 	}else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){
 		if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){
-			op2= FP_OP;
-		}else op2=INT_OP;
+		    oprnd_type= FP_OP;
+		}else oprnd_type=INT_OP;
 
 	}else{
 		if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){
-			op2= FP_OP;
-		}else op2=INT_OP;
+		    oprnd_type= FP_OP;
+		}else oprnd_type=INT_OP;
 	}
 }
 void ptx_instruction::set_mul_div_or_other_archop(){
-	op3=OTHER_OP;
+    sp_op=OTHER_OP;
 	if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){
 		if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){
 			switch(get_opcode()){
 				case MUL_OP:
 				case MAD_OP:
-					op3=FP_MUL_OP;
+				    sp_op=FP_MUL_OP;
 					break;
 				case DIV_OP:
-					op3=FP_DIV_OP;
+				    sp_op=FP_DIV_OP;
 					break;
 				case LG2_OP:
-					op3=FP_LG_OP;
+				    sp_op=FP_LG_OP;
 					break;
 				case RSQRT_OP:
 				case SQRT_OP:
-					op3=FP_SQRT_OP;
+				    sp_op=FP_SQRT_OP;
 					break;
 				case RCP_OP:
-               op3=FP_DIV_OP;
+				    sp_op=FP_DIV_OP;
 					break;
 				case SIN_OP:
 				case COS_OP:
-					op3=FP_SIN_OP;
+				    sp_op=FP_SIN_OP;
 					break;
 				case EX2_OP:
-					op3=FP_EXP_OP;
+				    sp_op=FP_EXP_OP;
 					break;
 				default:
 					if(op==ALU_OP)
-						op3=FP__OP;
+					    sp_op=FP__OP;
 					break;
 
 			}
@@ -520,21 +520,21 @@ void ptx_instruction::set_mul_div_or_other_archop(){
 			switch(get_opcode()){
 				case MUL24_OP:
 				case MAD24_OP:
-					op3=INT_MUL24_OP;
+				    sp_op=INT_MUL24_OP;
 				break;
 				case MUL_OP:
 				case MAD_OP:
 					if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE)
-						op3=INT_MUL32_OP;
+					    sp_op=INT_MUL32_OP;
 					else
-						op3=INT_MUL_OP;
+					    sp_op=INT_MUL_OP;
 				break;
 				case DIV_OP:
-					op3=INT_DIV_OP;
+				    sp_op=INT_DIV_OP;
 				break;
 				default:
 					if(op==ALU_OP)
-						op3=INT__OP;
+					    sp_op=INT__OP;
 					break;
 			}
 		}
@@ -585,7 +585,7 @@ void ptx_instruction::set_opcode_and_latency()
 	   	 }
 	}
    op = ALU_OP;
-   op5= NOT_TEX;
+   mem_op= NOT_TEX;
    initiation_interval = latency = 1;
    switch( m_opcode ) {
    case MOV_OP:
@@ -598,7 +598,7 @@ void ptx_instruction::set_opcode_and_latency()
    case ST_OP: op = STORE_OP; break;
    case BRA_OP: op = BRANCH_OP; break;
    case BREAKADDR_OP: op = BRANCH_OP; break;
-   case TEX_OP: op = LOAD_OP; op5=TEX; break;
+   case TEX_OP: op = LOAD_OP; mem_op=TEX; break;
    case ATOM_OP: op = LOAD_OP; break;
    case BAR_OP: op = BARRIER_OP; break;
    case MEMBAR_OP: op = MEMORY_BARRIER_OP; break;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 27fa2ca..011a21d 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -582,9 +582,9 @@ void shader_core_ctx::decode()
         m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
         if( pI1 ) {
             m_stats->m_num_decoded_insn[m_sid]++;
-            if(pI1->op2==INT_OP){
+            if(pI1->oprnd_type==INT_OP){
                 m_stats->m_num_INTdecoded_insn[m_sid]++;
-            }else if(pI1->op2==FP_OP) {
+            }else if(pI1->oprnd_type==FP_OP) {
             	m_stats->m_num_FPdecoded_insn[m_sid]++;
             }
            const warp_inst_t* pI2 = ptx_fetch_inst(pc+pI1->isize);
@@ -592,9 +592,9 @@ void shader_core_ctx::decode()
                m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1,pI2);
                m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
                m_stats->m_num_decoded_insn[m_sid]++;
-               if(pI2->op2==INT_OP){
+               if(pI2->oprnd_type==INT_OP){
                    m_stats->m_num_INTdecoded_insn[m_sid]++;
-               }else if(pI2->op2==FP_OP) {
+               }else if(pI2->oprnd_type==FP_OP) {
             	   m_stats->m_num_FPdecoded_insn[m_sid]++;
                }
            }
@@ -1185,11 +1185,11 @@ void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
       printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", 
              inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); 
    #endif
-  if(inst.op4==SP__OP)
+  if(inst.op_pipe==SP__OP)
 	  m_stats->m_num_sp_committed[m_sid]++;
-  else if(inst.op4==SFU__OP)
+  else if(inst.op_pipe==SFU__OP)
 	  m_stats->m_num_sfu_committed[m_sid]++;
-  else if(inst.op4==MEM__OP)
+  else if(inst.op_pipe==MEM__OP)
 	  m_stats->m_num_mem_committed[m_sid]++;
 
   if(m_config->gpgpu_clock_gated_lanes==false)
@@ -1427,7 +1427,7 @@ void sfu::issue( register_set& source_reg )
     warp_inst_t** ready_reg = source_reg.get_ready();
 	//m_core->incexecstat((*ready_reg));
 
-	(*ready_reg)->op4=SFU__OP;
+	(*ready_reg)->op_pipe=SFU__OP;
 	m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
 	pipelined_simd_unit::issue(source_reg);
 }
@@ -1463,7 +1463,7 @@ void sp_unit :: issue(register_set& source_reg)
 {
     warp_inst_t** ready_reg = source_reg.get_ready();
 	//m_core->incexecstat((*ready_reg));
-	(*ready_reg)->op4=SP__OP;
+	(*ready_reg)->op_pipe=SP__OP;
 	m_core->incsp_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
 	pipelined_simd_unit::issue(source_reg);
 }
@@ -1598,8 +1598,6 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
 void ldst_unit:: issue( register_set &reg_set )
 {
 	warp_inst_t* inst = *(reg_set.get_ready());
-   // stat collection
-   m_core->mem_instruction_stats(*inst);
 
    // record how many pending register writes/memory accesses there are for this instruction
    assert(inst->empty() == false);
@@ -1615,7 +1613,8 @@ void ldst_unit:: issue( register_set &reg_set )
    }
 
 
-	inst->op4=MEM__OP;
+	inst->op_pipe=MEM__OP;
+	// stat collection
 	m_core->mem_instruction_stats(*inst);
 	m_core->incmem_stat(m_core->get_config()->warp_size,1);
 	pipelined_simd_unit::issue(reg_set);
@@ -2015,18 +2014,19 @@ void warp_inst_t::print( FILE *fout ) const
 }
 void shader_core_ctx::incexecstat(warp_inst_t *&inst)
 {
-	if(inst->op5==TEX)
+	if(inst->mem_op==TEX)
 		inctex_stat(inst->active_count(),1);
 
-	switch(inst->op3){
+    // Latency numbers for next operations are used to scale the power values
+    // for special operations, according observations from microbenchmarking
+    // TODO: put these numbers in the xml configuration
+
+	switch(inst->sp_op){
 	case INT__OP:
 		incialu_stat(inst->active_count(),25);
 		break;
 	case INT_MUL_OP:
-		if(m_config->gpgpu_shader_registers==32768) //i.e. FERMI
-			incimul_stat(inst->active_count(),7.2);
-		else
-			incimul_stat(inst->active_count(),16);
+		incimul_stat(inst->active_count(),7.2);
 		break;
 	case INT_MUL24_OP:
 		incimul24_stat(inst->active_count(),4.2);
@@ -2038,52 +2038,26 @@ void shader_core_ctx::incexecstat(warp_inst_t *&inst)
 		incidiv_stat(inst->active_count(),40);
 		break;
 	case FP__OP:
-		if(m_config->gpgpu_shader_registers==32768)
 		incfpalu_stat(inst->active_count(),1);
-		else
-		incfpalu_stat(inst->active_count(),1.7);
 		break;
 	case FP_MUL_OP:
-		if(m_config->gpgpu_shader_registers==32768)
-		incfpmul_stat(inst->active_count(),1.8);
-		else
 		incfpmul_stat(inst->active_count(),1.8);
 		break;
 	case FP_DIV_OP:
-		if(m_config->gpgpu_shader_registers==32768)
 		incfpdiv_stat(inst->active_count(),48);
-		else 
-		incfpdiv_stat(inst->active_count(),22);
 		break;
 	case FP_SQRT_OP:
-		if(m_config->gpgpu_shader_registers==32768)
 		inctrans_stat(inst->active_count(),25);
-		else
-		inctrans_stat(inst->active_count(),8);
-
 		break;
 	case FP_LG_OP:
-		if (m_config->gpgpu_shader_registers==32768)
 		inctrans_stat(inst->active_count(),35);
-		else
-		inctrans_stat(inst->active_count(),0.3);
 		break;
 	case FP_SIN_OP:
-		if(m_config->gpgpu_shader_registers==32768)
 		inctrans_stat(inst->active_count(),12);
-		else 
-		inctrans_stat(inst->active_count(),40);
-
 		break;
 	case FP_EXP_OP:
-		if(m_config->gpgpu_shader_registers==32768)
 		inctrans_stat(inst->active_count(),35);
-		else 
-		inctrans_stat(inst->active_count(),9);
-
 		break;
-
-
 	default:
 		break;
 	}
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index f2d38a0..f4d300b 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -556,10 +556,10 @@ private:
           else if( m_cu ) return m_cu->get_active_mask();
           else abort();
       }
-      unsigned get_op3() const
+      unsigned get_sp_op() const
       {
-          if( m_warp ) return m_warp->op3;
-          else if( m_cu ) return m_cu->get_op3();
+          if( m_warp ) return m_warp->sp_op;
+          else if( m_cu ) return m_cu->get_sp_op();
           else abort();
       }
       unsigned get_oc_id() const { return m_cu->get_id(); }
@@ -754,7 +754,7 @@ private:
       unsigned get_warp_id() const { return m_warp_id; }
       unsigned get_active_count() const { return m_warp->active_count(); }
       const active_mask_t & get_active_mask() const { return m_warp->get_active_mask(); }
-      unsigned get_op3() const { return m_warp->op3; }
+      unsigned get_sp_op() const { return m_warp->sp_op; }
       unsigned get_id() const { return m_cuid; } // returns CU hw id
 
       // modifiers
@@ -1871,8 +1871,6 @@ public:
     }
     virtual void push(mem_fetch *mf)
     {
-        if( !mf->get_inst().empty() )
-            m_core->mem_instruction_stats(mf->get_inst()); // not I$-fetch
         if ( mf && mf->isatomic() )
             mf->do_atomic(); // execute atomic inside the "memory subsystem"
         m_cluster->push_response_fifo(mf);