Merge remote-tracking branch 'localpub/dev' into dev

5 files changed, 101 insertions, 61 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 39e2b7e..75dd3c8 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -57,11 +57,11 @@ int g_debug_execution = 0;
 // Output debug information to file options
 
 void cuda_sim::ptx_opcocde_latency_options(option_parser_t opp) {
-  option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR,
-                         &opcode_latency_int,
-                         "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>"
-                         "Default 1,1,19,25,145",
-                         "1,1,19,25,145");
+  option_parser_register(
+      opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
+      "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>"
+      "Default 1,1,19,25,145,32",
+      "1,1,19,25,145,32");
   option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR,
                          &opcode_latency_fp,
                          "Opcode latencies for single precision floating "
@@ -86,9 +86,9 @@ void cuda_sim::ptx_opcocde_latency_options(option_parser_t opp) {
                          "64");
   option_parser_register(
       opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
-      "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
-      "Default 1,1,4,4,32",
-      "1,1,4,4,32");
+      "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>"
+      "Default 1,1,4,4,32,4",
+      "1,1,4,4,32,4");
   option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR,
                          &opcode_initiation_fp,
                          "Opcode initiation intervals for single precision "
@@ -682,12 +682,12 @@ void ptx_instruction::set_bar_type() {
 }
 
 void ptx_instruction::set_opcode_and_latency() {
-  unsigned int_latency[5];
+  unsigned int_latency[6];
   unsigned fp_latency[5];
   unsigned dp_latency[5];
   unsigned sfu_latency;
   unsigned tensor_latency;
-  unsigned int_init[5];
+  unsigned int_init[6];
   unsigned fp_init[5];
   unsigned dp_init[5];
   unsigned sfu_init;
@@ -698,10 +698,11 @@ void ptx_instruction::set_opcode_and_latency() {
    * [2] MUL
    * [3] MAD
    * [4] DIV
+   * [5] SHFL
    */
-  sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
+  sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u,%u",
          &int_latency[0], &int_latency[1], &int_latency[2], &int_latency[3],
-         &int_latency[4]);
+         &int_latency[4], &int_latency[5]);
   sscanf(gpgpu_ctx->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
          &fp_latency[0], &fp_latency[1], &fp_latency[2], &fp_latency[3],
          &fp_latency[4]);
@@ -710,8 +711,9 @@ void ptx_instruction::set_opcode_and_latency() {
          &dp_latency[4]);
   sscanf(gpgpu_ctx->func_sim->opcode_latency_sfu, "%u", &sfu_latency);
   sscanf(gpgpu_ctx->func_sim->opcode_latency_tensor, "%u", &tensor_latency);
-  sscanf(gpgpu_ctx->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u",
-         &int_init[0], &int_init[1], &int_init[2], &int_init[3], &int_init[4]);
+  sscanf(gpgpu_ctx->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u,%u",
+         &int_init[0], &int_init[1], &int_init[2], &int_init[3], &int_init[4],
+         &int_init[5]);
   sscanf(gpgpu_ctx->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u",
          &fp_init[0], &fp_init[1], &fp_init[2], &fp_init[3], &fp_init[4]);
   sscanf(gpgpu_ctx->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u",
@@ -940,8 +942,8 @@ void ptx_instruction::set_opcode_and_latency() {
       op = TENSOR_CORE_OP;
       break;
     case SHFL_OP:
-      latency = 4;
-      initiation_interval = 4;
+      latency = int_latency[5];
+      initiation_interval = int_init[5];
       break;
     default:
       break;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index a01c3c6..b38f783 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -298,6 +298,7 @@ ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND
 statement_block: LEFT_BRACE statement_list RIGHT_BRACE 
 
 statement_list: directive_statement { recognizer->add_directive(); }
+    | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); }
 	| instruction_statement { recognizer->add_instruction(); }
 	| statement_list directive_statement { recognizer->add_directive(); }
 	| statement_list instruction_statement { recognizer->add_instruction(); }
@@ -414,6 +415,23 @@ initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { recognizer->add_array_in
 literal_list: literal_operand
 	| literal_list COMMA literal_operand;
 
+// TODO: This is currently hardcoded to handle and ignore one specific case
+// that all prototype statements follow in the PTX from Pytorch. As a
+// workaround, this parses and ignores both the prototype declaration 
+// and calling of the prototype (which conveniently comes right after the 
+// declaration for all cases.) This should be changed to handle both 
+// declaring the prototype, and actually calling it.
+prototype_block: prototype_decl prototype_call
+
+prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON 
+	      
+prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
+	      | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
+
+prototype_param: /* empty */
+	       | PARAM_DIRECTIVE B64_TYPE IDENTIFIER
+	       | PARAM_DIRECTIVE B32_TYPE IDENTIFIER
+
 instruction_statement:  instruction SEMI_COLON
 	| IDENTIFIER COLON { recognizer->add_label($1); }
 	| pred_spec instruction SEMI_COLON;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index a638f5c..b596c0d 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3140,7 +3140,7 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const {
 void shader_core_config::set_pipeline_latency() {
   // calculate the max latency  based on the input
 
-  unsigned int_latency[5];
+  unsigned int_latency[6];
   unsigned fp_latency[5];
   unsigned dp_latency[5];
   unsigned sfu_latency;
@@ -3152,10 +3152,11 @@ void shader_core_config::set_pipeline_latency() {
    * [2] MUL
    * [3] MAD
    * [4] DIV
+   * [5] SHFL
    */
-  sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
+  sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u,%u",
          &int_latency[0], &int_latency[1], &int_latency[2], &int_latency[3],
-         &int_latency[4]);
+         &int_latency[4], &int_latency[5]);
   sscanf(gpgpu_ctx->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
          &fp_latency[0], &fp_latency[1], &fp_latency[2], &fp_latency[3],
          &fp_latency[4]);
@@ -3170,7 +3171,7 @@ void shader_core_config::set_pipeline_latency() {
   max_sfu_latency = std::max(dp_latency[4], sfu_latency);
   // assume that the max operation has the max latency
   max_sp_latency = fp_latency[1];
-  max_int_latency = int_latency[1];
+  max_int_latency = std::max(int_latency[1], int_latency[5]);
   max_dp_latency = dp_latency[1];
   max_tensor_core_latency = tensor_latency;
 }
diff --git a/src/stream_manager.cc b/src/stream_manager.cc
index 48a1edc..e99bf87 100644
--- a/src/stream_manager.cc
+++ b/src/stream_manager.cc
@@ -181,13 +181,17 @@ bool stream_operation::do_operation(gpgpu_sim *gpu) {
       m_event->update(gpu->gpu_tot_sim_cycle, wallclock);
       m_stream->record_next_done();
     } break;
-    case stream_wait_event: {
+    case stream_wait_event:
       // only allows next op to go if event is done
       // otherwise stays in the stream queue
       printf("stream wait event processing...\n");
-      if (m_event->done()) printf("stream wait event done\n");
-      m_stream->record_next_done();
-    } break;
+      if (m_event->num_updates() >= m_cnt) {
+        printf("stream wait event done\n");
+        m_stream->record_next_done();
+      } else {
+        return false;
+      }
+      break;
     default:
       abort();
   }
@@ -231,6 +235,7 @@ stream_manager::stream_manager(gpgpu_sim *gpu, bool cuda_launch_blocking) {
   m_service_stream_zero = false;
   m_cuda_launch_blocking = cuda_launch_blocking;
   pthread_mutex_init(&m_lock, NULL);
+  m_last_stream = m_streams.begin();
 }
 
 bool stream_manager::operation(bool *sim) {
@@ -326,10 +331,18 @@ stream_operation stream_manager::front() {
       m_service_stream_zero = false;
     }
   }
-
   if (!m_service_stream_zero) {
-    std::list<struct CUstream_st *>::iterator s;
-    for (s = m_streams.begin(); s != m_streams.end(); s++) {
+    std::list<struct CUstream_st *>::iterator s = m_last_stream;
+    if (m_last_stream == m_streams.end()) {
+      s = m_streams.begin();
+    } else {
+      s++;
+    }
+    for (size_t ii = 0; ii < m_streams.size(); ii++, s++) {
+      if (s == m_streams.end()) {
+        s = m_streams.begin();
+      }
+      m_last_stream = s;
       CUstream_st *stream = *s;
       if (!stream->busy() && !stream->empty()) {
         result = stream->next();
@@ -364,6 +377,7 @@ void stream_manager::destroy_stream(CUstream_st *stream) {
     }
   }
   delete stream;
+  m_last_stream = m_streams.begin();
   pthread_mutex_unlock(&m_lock);
 }
 
diff --git a/src/stream_manager.h b/src/stream_manager.h
index d543e68..afcbb0e 100644
--- a/src/stream_manager.h
+++ b/src/stream_manager.h
@@ -44,6 +44,43 @@
 //    unsigned m_pending_streams;
 //};
 
+struct CUevent_st {
+ public:
+  CUevent_st(bool blocking) {
+    m_uid = ++m_next_event_uid;
+    m_blocking = blocking;
+    m_updates = 0;
+    m_wallclock = 0;
+    m_gpu_tot_sim_cycle = 0;
+    m_issued = 0;
+    m_done = false;
+  }
+  void update(double cycle, time_t clk) {
+    m_updates++;
+    m_wallclock = clk;
+    m_gpu_tot_sim_cycle = cycle;
+    m_done = true;
+  }
+  // void set_done() { assert(!m_done); m_done=true; }
+  int get_uid() const { return m_uid; }
+  unsigned num_updates() const { return m_updates; }
+  bool done() const { return m_updates == m_issued; }
+  time_t clock() const { return m_wallclock; }
+  void issue() { m_issued++; }
+  unsigned int num_issued() const { return m_issued; }
+
+ private:
+  int m_uid;
+  bool m_blocking;
+  bool m_done;
+  int m_updates;
+  unsigned int m_issued;
+  time_t m_wallclock;
+  double m_gpu_tot_sim_cycle;
+
+  static int m_next_event_uid;
+};
+
 enum stream_operation_type {
   stream_no_op,
   stream_memcpy_host_to_device,
@@ -106,6 +143,7 @@ class stream_operation {
     m_kernel = NULL;
     m_type = stream_wait_event;
     m_event = e;
+    m_cnt = m_event->num_issued();
     m_stream = stream;
     m_done = false;
   }
@@ -184,40 +222,6 @@ class stream_operation {
   kernel_info_t *m_kernel;
   struct CUevent_st *m_event;
 };
-
-struct CUevent_st {
- public:
-  CUevent_st(bool blocking) {
-    m_uid = ++m_next_event_uid;
-    m_blocking = blocking;
-    m_updates = 0;
-    m_wallclock = 0;
-    m_gpu_tot_sim_cycle = 0;
-    m_done = false;
-  }
-  void update(double cycle, time_t clk) {
-    m_updates++;
-    m_wallclock = clk;
-    m_gpu_tot_sim_cycle = cycle;
-    m_done = true;
-  }
-  // void set_done() { assert(!m_done); m_done=true; }
-  int get_uid() const { return m_uid; }
-  unsigned num_updates() const { return m_updates; }
-  bool done() const { return m_done; }
-  time_t clock() const { return m_wallclock; }
-
- private:
-  int m_uid;
-  bool m_blocking;
-  bool m_done;
-  int m_updates;
-  time_t m_wallclock;
-  double m_gpu_tot_sim_cycle;
-
-  static int m_next_event_uid;
-};
-
 struct CUstream_st {
  public:
   CUstream_st();
@@ -272,6 +276,7 @@ class stream_manager {
   CUstream_st m_stream_zero;
   bool m_service_stream_zero;
   pthread_mutex_t m_lock;
+  std::list<struct CUstream_st *>::iterator m_last_stream;
 };
 
 #endif