fixing reformatting

6 files changed, 63 insertions, 57 deletions

diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 4a6e02a..46534ab 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -65,11 +65,7 @@ enum FuncCache {
   FuncCachePreferL1 = 2
 };
 
-enum AdaptiveCache
-{
-  FIXED = 0,
-  VOLTA = 1
-};
+enum AdaptiveCache { FIXED = 0, VOLTA = 1 };
 
 #ifdef __cplusplus
 
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 6ae57a1..655d790 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -144,11 +144,16 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr,
       if (m_n_channel == 32) {
         std::bitset<64> a(tlx->row);
         std::bitset<5> chip(tlx->chip);
-        chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ a[0] ^ chip[0];
-        chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ a[1] ^ chip[1];
-        chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ a[0] ^ chip[2];
-        chip[3] = a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3];
-        chip[4] = a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4];
+        chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^
+                  a[0] ^ chip[0];
+        chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^
+                  a[1] ^ chip[1];
+        chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^
+                  a[0] ^ chip[2];
+        chip[3] =
+            a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3];
+        chip[4] =
+            a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4];
         tlx->chip = chip.to_ulong();
 
       } else { /* Else incorrect number of channels for the hashing function */
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 5cdeeb1..af22c4c 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -59,9 +59,9 @@ const char *cache_fail_status_str(enum cache_reservation_fail_reason status) {
 }
 
 unsigned l1d_cache_config::set_bank(new_addr_type addr) const {
-  //For sector cache, we select one sector per bank (sector interleaving)
-  //This is what was found in Volta (one sector per bank, sector interleaving)
-  //otherwise, line interleaving
+  // For sector cache, we select one sector per bank (sector interleaving)
+  // This is what was found in Volta (one sector per bank, sector interleaving)
+  // otherwise, line interleaving
   if (m_cache_type == SECTOR)
     return (addr >> m_sector_sz_log2) & (l1_banks - 1);
   else
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 7554b3f..2a37876 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -677,9 +677,8 @@ class cache_config {
     assert(m_valid);
     return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
   }
-  unsigned get_max_assoc() const
-  {
-    assert( m_valid );
+  unsigned get_max_assoc() const {
+    assert(m_valid);
     return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * original_m_assoc;
   }
   void print(FILE *fp) const {
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 5ded780..dd20776 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -319,8 +319,7 @@ void shader_core_config::reg_options(class OptionParser *opp) {
       opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
       "Size of shared memory per shader core (default 16kB)", "16384");
   option_parser_register(opp, "-adaptive_cache_config", OPT_BOOL,
-                         &adaptive_cache_config, "adaptive_cache_config",
-                         "0");
+                         &adaptive_cache_config, "adaptive_cache_config", "0");
   option_parser_register(
       opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
       "Size of shared memory per shader core (default 16kB)", "16384");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 16bc770..ef38593 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3082,49 +3082,56 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const {
     abort();
   }
 
-    if(adaptive_cache_config && !k.cache_config_set) {
-    	//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
-    	unsigned total_shmed = kernel_info->smem * result;
-    	assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
-    	//assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
-    	//assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
-    	if(total_shmed < gpgpu_shmem_size){
-    		switch (adaptive_cache_config) {
-    		case FIXED:
-    			break;
-    		case VOLTA: {
-    			//For Volta, we assign the remaining shared memory to L1 cache
-    			//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
-    			assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
-
-    			//To Do: make it flexible and not tuned to 9KB share memory
-    			unsigned max_assoc = m_L1D_config.get_max_assoc();
-    			if(total_shmed == 0)
-    				m_L1D_config.set_assoc(max_assoc);  //L1 is 128KB and shd=0
-    			else if(total_shmed > 0 && total_shmed <= 8192)
-    				m_L1D_config.set_assoc(0.9375 * max_assoc);  //L1 is 120KB and shd=8KB
-    			else if(total_shmed > 8192 && total_shmed <= 16384)
-    				m_L1D_config.set_assoc(0.875 * max_assoc);  //L1 is 112KB and shd=16KB
-    			else if(total_shmed > 16384 && total_shmed <= 32768)
-    				m_L1D_config.set_assoc(0.75 * max_assoc);  //L1 is 96KB and shd=32KB
-    			else if(total_shmed > 32768 && total_shmed <= 65536)
-    				m_L1D_config.set_assoc(0.5 * max_assoc);	//L1 is 64KB and shd=64KB
-    			else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
-    				m_L1D_config.set_assoc(0.25 * max_assoc); //L1 is 32KB and shd=96KB
-    			else
-    				assert(0);
-    			break;
-    		}
-    		default:
-    			assert(0);
-    		}
+  if (adaptive_cache_config && !k.cache_config_set) {
+    // For more info about adaptive cache, see
+    // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+    unsigned total_shmed = kernel_info->smem * result;
+    assert(total_shmed >= 0 && total_shmed <= gpgpu_shmem_size);
+    // assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+    // assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
+    if (total_shmed < gpgpu_shmem_size) {
+      switch (adaptive_cache_config) {
+        case FIXED:
+          break;
+        case VOLTA: {
+          // For Volta, we assign the remaining shared memory to L1 cache
+          // For more info about adaptive cache, see
+          // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+          assert(gpgpu_shmem_size == 98304);  // Volta has 96 KB shared
 
-			printf ("GPGPU-Sim: Reconfigure L1 cache to %uKB\n", m_L1D_config.get_total_size_inKB());
-    	}
+          // To Do: make it flexible and not tuned to 9KB share memory
+          unsigned max_assoc = m_L1D_config.get_max_assoc();
+          if (total_shmed == 0)
+            m_L1D_config.set_assoc(max_assoc);  // L1 is 128KB and shd=0
+          else if (total_shmed > 0 && total_shmed <= 8192)
+            m_L1D_config.set_assoc(0.9375 *
+                                   max_assoc);  // L1 is 120KB and shd=8KB
+          else if (total_shmed > 8192 && total_shmed <= 16384)
+            m_L1D_config.set_assoc(0.875 *
+                                   max_assoc);  // L1 is 112KB and shd=16KB
+          else if (total_shmed > 16384 && total_shmed <= 32768)
+            m_L1D_config.set_assoc(0.75 * max_assoc);  // L1 is 96KB and
+                                                       // shd=32KB
+          else if (total_shmed > 32768 && total_shmed <= 65536)
+            m_L1D_config.set_assoc(0.5 * max_assoc);  // L1 is 64KB and shd=64KB
+          else if (total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+            m_L1D_config.set_assoc(0.25 * max_assoc);  // L1 is 32KB and
+                                                       // shd=96KB
+          else
+            assert(0);
+          break;
+        }
+        default:
+          assert(0);
+      }
 
-    	k.cache_config_set = true;
+      printf("GPGPU-Sim: Reconfigure L1 cache to %uKB\n",
+             m_L1D_config.get_total_size_inKB());
     }
 
+    k.cache_config_set = true;
+  }
+
   return result;
 }