add more statistics and chaging Pascal config

10 files changed, 31 insertions, 13 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 51265fd..d2a155c 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -314,7 +314,7 @@ void warp_inst_t::generate_mem_accesses()
         break;
 
     case global_space: case local_space: case param_space_local:
-    	 if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) {
+    	 if( m_config->gpgpu_coalesce_arch >= 13 && m_config->gpgpu_coalesce_arch <= 62) {
             if(isatomic())
                 memory_coalescing_arch_atomic(is_write, access_type);
             else
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 7ed7b6f..de37f64 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -570,9 +570,10 @@ bool dram_t::issue_col_command(int j)
           bkgrp[grp]->RTPLc = m_config->tRTPL;
           issued = true;
           if(bk[j]->mrq->data->get_access_type() == L2_WR_ALLOC_R)
-                n_rd_L2_A++;
+        	  n_rd_L2_A++;
           else
                 n_rd++;
+
           bwutil += m_config->BL/m_config->data_command_freq_ratio;
           bwutil_partial += m_config->BL/m_config->data_command_freq_ratio;
           bk[j]->n_access++;
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index 7a140c5..ac4c827 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -220,6 +220,8 @@ void dram_t::scheduler_frfcfs()
             bk[b]->mrq = req;
             if (m_config->gpgpu_memlatency_stat) {
                mrq_latency = gpu_sim_cycle + gpu_tot_sim_cycle - bk[b]->mrq->timestamp;
+               m_stats->tot_mrq_latency += mrq_latency;
+               m_stats->tot_mrq_num++;
                bk[b]->mrq->timestamp = gpu_tot_sim_cycle + gpu_sim_cycle;
                m_stats->mrq_lat_table[LOGB2(mrq_latency)]++;
                if (mrq_latency > m_stats->max_mrq_latency) {
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index d199cca..32c2bb1 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -333,8 +333,10 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf)
 void tag_array::flush() 
 {
     for (unsigned i=0; i < m_config.get_num_lines(); i++)
+    	if(m_lines[i]->is_modified_line()) {
     	for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
     		m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
+    	}
 }
 
 float tag_array::windowed_miss_rate( ) const
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 6179d46..0e06c5c 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1412,7 +1412,7 @@ void gpgpu_sim::cycle()
             if (mf) {
                 unsigned response_size = mf->get_is_write()?mf->get_ctrl_size():mf->size();
                 if ( ::icnt_has_buffer( m_shader_config->mem2device(i), response_size ) ) {
-                    if (!mf->get_is_write()) 
+                    //if (!mf->get_is_write())
                        mf->set_return_timestamp(gpu_sim_cycle+gpu_tot_sim_cycle);
                     mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle);
                     ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size );
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 52c4643..043fcee 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -199,7 +199,7 @@ struct memory_config {
       assert(nbkgrp>0 && "Number of bank groups cannot be zero");
       tRCDWR = tRCD-(WL+1);
       tRTW = (CL+(BL/data_command_freq_ratio)+2-WL);
-      tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); 
+      tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR);
       tWTP = (WL+(BL/data_command_freq_ratio)+tWR);
       dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition 
 
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index cac59f1..8fbf448 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -628,6 +628,7 @@ std::vector<mem_fetch*> memory_sub_partition::breakdown_request_to_sector_reques
 void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle )
 {
     if (m_req) {
+    	m_stats->memlatstat_icnt2mem_pop(m_req);
     	std::vector<mem_fetch*> reqs;
     	if(m_config->m_L2_config.m_cache_type == SECTOR)
     		reqs = breakdown_request_to_sector_requests(m_req);
@@ -637,7 +638,6 @@ void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle )
     	for(unsigned i=0; i<reqs.size(); ++i) {
     		mem_fetch* req = reqs[i];
 			m_request_tracker.insert(req);
-			m_stats->memlatstat_icnt2mem_pop(req);
 			if( req->istexture() ) {
 				m_icnt_L2_queue->push(req);
 				req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index fde0eff..35d6d84 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -75,6 +75,10 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf
    max_mf_latency = 0;
    max_icnt2mem_latency = 0;
    max_icnt2sh_latency = 0;
+   tot_icnt2mem_latency = 0;
+   tot_icnt2sh_latency = 0;
+   tot_mrq_num = 0;
+   tot_mrq_latency = 0;
    memset(mrq_lat_table, 0, sizeof(unsigned)*32);
    memset(dq_lat_table, 0, sizeof(unsigned)*32);
    memset(mf_lat_table, 0, sizeof(unsigned)*32);
@@ -158,6 +162,7 @@ void memory_stats_t::memlatstat_read_done(mem_fetch *mf)
          mf_max_lat_table[mf->get_tlx_addr().chip][mf->get_tlx_addr().bk] = mf_latency;
       unsigned icnt2sh_latency;
       icnt2sh_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_return_timestamp();
+      tot_icnt2sh_latency += icnt2sh_latency;
       icnt2sh_lat_table[LOGB2(icnt2sh_latency)]++;
       if (icnt2sh_latency > max_icnt2sh_latency)
          max_icnt2sh_latency = icnt2sh_latency;
@@ -191,6 +196,7 @@ void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf)
    if (m_memory_config->gpgpu_memlatency_stat) {
       unsigned icnt2mem_latency;
       icnt2mem_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_timestamp();
+      tot_icnt2mem_latency += icnt2mem_latency;
       icnt2mem_lat_table[LOGB2(icnt2mem_latency)]++;
       if (icnt2mem_latency > max_icnt2mem_latency)
          max_icnt2mem_latency = icnt2mem_latency;
@@ -216,14 +222,17 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk )
    unsigned max_bank_accesses, min_bank_accesses, max_chip_accesses, min_chip_accesses;
 
    if (m_memory_config->gpgpu_memlatency_stat) {
+	   printf("maxmflatency = %d \n", max_mf_latency);
+	   printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency);
       printf("maxmrqlatency = %d \n", max_mrq_latency);
-      printf("maxdqlatency = %d \n", max_dq_latency);
-      printf("maxmflatency = %d \n", max_mf_latency);
+      //printf("maxdqlatency = %d \n", max_dq_latency);
+      printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency);
       if (num_mfs) {
          printf("averagemflatency = %lld \n", mf_total_lat/num_mfs);
+         printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs);
+         printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num);
+         printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs);
       }
-      printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency);
-      printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency);
       printf("mrq_lat_table:");
       for (i=0; i< 32; i++) {
          printf("%d \t", mrq_lat_table[i]);
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 4968a3b..5b89202 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -56,6 +56,10 @@ public:
    unsigned max_dq_latency;
    unsigned max_mf_latency;
    unsigned max_icnt2mem_latency;
+   unsigned long long int tot_icnt2mem_latency;
+   unsigned long long int tot_icnt2sh_latency;
+   unsigned long long int tot_mrq_latency;
+   unsigned long long int tot_mrq_num;
    unsigned max_icnt2sh_latency;
    unsigned mrq_lat_table[32];
    unsigned dq_lat_table[32];
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c14e19f..bf482fb 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1458,7 +1458,7 @@ ldst_unit::process_cache_access( cache_t* cache,
         if( !write_sent ) 
             delete mf;
     } else if ( status == RESERVATION_FAIL ) {
-        result = COAL_STALL;
+        result = BK_CONF;
         assert( !read_sent );
         assert( !write_sent );
         delete mf;
@@ -1467,8 +1467,8 @@ ldst_unit::process_cache_access( cache_t* cache,
         //inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns
         inst.accessq_pop_back();
     }
-    if( !inst.accessq_empty() )
-        result = BK_CONF;
+    if( !inst.accessq_empty() && result == NO_RC_FAIL)
+        result = COAL_STALL;
     return result;
 }
 
@@ -1563,7 +1563,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
        assert( CACHE_UNDEFINED != inst.cache_op );
        stall_cond = process_memory_access_queue(m_L1D,inst);
    }
-   if( !inst.accessq_empty() ) 
+   if( !inst.accessq_empty() && stall_cond == NO_RC_FAIL)
        stall_cond = COAL_STALL;
    if (stall_cond != NO_RC_FAIL) {
       stall_reason = stall_cond;