diff options
| -rw-r--r-- | configs/tested-cfgs/TITAN_V/gpgpusim.config | 173 | ||||
| -rw-r--r-- | configs/tested-cfgs/TITAN_V/trace.config | 18 |
2 files changed, 0 insertions, 191 deletions
diff --git a/configs/tested-cfgs/TITAN_V/gpgpusim.config b/configs/tested-cfgs/TITAN_V/gpgpusim.config deleted file mode 100644 index 8b5cb20..0000000 --- a/configs/tested-cfgs/TITAN_V/gpgpusim.config +++ /dev/null @@ -1,173 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# Device Limits --gpgpu_stack_size_limit 1024 --gpgpu_heap_size_limit 8388608 --gpgpu_runtime_sync_depth_limit 2 --gpgpu_runtime_pending_launch_count_limit 2048 --gpgpu_kernel_launch_latency 6745 --gpgpu_TB_launch_latency 0 - -# Compute Capability --gpgpu_compute_capability_major 7 --gpgpu_compute_capability_minor 0 - -# PTX execution-driven --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 80 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 2 - -# clock domains -#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> --gpgpu_clock_domains 1200:1200:1200:850 - -# shader core pipeline config --gpgpu_shader_registers 65536 --gpgpu_registers_per_block 65536 --gpgpu_occupancy_sm_number 70 - --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 --gpgpu_num_int_units 4 --gpgpu_tensor_core_avail 1 --gpgpu_num_tensor_core_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit --ptx_opcode_latency_int 4,4,4,4,21 --ptx_opcode_initiation_int 2,2,2,2,2 --ptx_opcode_latency_fp 4,4,4,4,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,8,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 21 --ptx_opcode_initiation_sfu 8 --ptx_opcode_latency_tesnor 35 --ptx_opcode_initiation_tensor 32 - -# sub core model: in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --gpgpu_sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --gpgpu_enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# register banks --gpgpu_num_reg_banks 16 --gpgpu_reg_file_port_throughput 2 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 70 - -# warp scheduling --gpgpu_num_sched_per_core 4 --gpgpu_scheduler gto -# a warp scheduler issue mode --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -## L1/shared memory configuration -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> -# ** Optional parameter - Required when mshr_type==Texture Fifo -# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache --gpgpu_adaptive_cache_config 1 --gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:64,16:0,32 --gpgpu_shmem_size 98304 --gpgpu_shmem_sizeDefault 98304 --gpgpu_shmem_per_block 49152 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 33 --gpgpu_smem_latency 27 --gpgpu_flush_l1_cache 1 - -# L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --gpgpu_perf_sim_memcpy 1 --gpgpu_memory_partition_indexing 0 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 --gpgpu_inst_fetch_throughput 4 -# 128 KB Tex -# Note, TEX is deprected since Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod --gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 --gpgpu_perfect_inst_const_cache 1 - -# interconnection -# use built-in local xbar --network_mode 2 --icnt_in_buffer_limit 512 --icnt_out_buffer_limit 512 --icnt_subnets 2 --icnt_flit_size 40 --icnt_arbiter_algo 1 - -# memory partition latency config --gpgpu_l2_rop_latency 177 --dram_latency 103 - -# dram sched config --gpgpu_dram_scheduler 1 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# dram model config --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Mem timing --gpgpu_dram_timing_opt nbk=16:CCD=1:RRD=4:RCD=12:RAS=29:RP=12:RC=40:CL=12:WL=2:CDLR=3:WR=11:nbkgrp=4:CCDL=2:RTPL=4 --dram_dual_bus_interface 1 - -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-dram_seperate_write_queue_enable 1 -#-dram_write_queue_size 64:56:32 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model --power_simulation_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/tested-cfgs/TITAN_V/trace.config b/configs/tested-cfgs/TITAN_V/trace.config deleted file mode 100644 index 6e193f7..0000000 --- a/configs/tested-cfgs/TITAN_V/trace.config +++ /dev/null @@ -1,18 +0,0 @@ --trace_opcode_latency_initiation_int 4,2 --trace_opcode_latency_initiation_sp 4,2 --trace_opcode_latency_initiation_dp 8,4 --trace_opcode_latency_initiation_sfu 21,8 --trace_opcode_latency_initiation_tensor 2,2 - -#execute branch insts on spec unit 1 -#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME> --specialized_unit_1 1,4,4,4,4,BRA --trace_opcode_latency_initiation_spec_op_1 4,4 - -#TEX unit, make fixed latency for all tex insts --specialized_unit_2 1,4,200,4,4,TEX --trace_opcode_latency_initiation_spec_op_2 200,4 - -#tensor unit --specialized_unit_3 1,4,2,4,4,TENSOR --trace_opcode_latency_initiation_spec_op_3 2,2 |