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-rw-r--r--configs/4.x-cfgs/SM7_TITANV/gpgpusim.config19
-rw-r--r--src/abstract_hardware_model.cc2
-rw-r--r--src/abstract_hardware_model.h2
-rw-r--r--src/gpgpu-sim/gpu-cache.cc9
-rw-r--r--src/gpgpu-sim/gpu-cache.h31
-rw-r--r--src/gpgpu-sim/gpu-sim.cc3
-rw-r--r--src/gpgpu-sim/shader.cc29
-rw-r--r--src/gpgpu-sim/shader.h2
8 files changed, 80 insertions, 17 deletions
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index cc4c931..a7056db 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -65,19 +65,21 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 64KB DL1 and 64KB shared memory
--gpgpu_cache:dl1 S:4:128:128,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1 S:4:128:192,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 32768
--gpgpu_shmem_size_PrefShared 98304
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
-gmem_skip_L1D 0
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
-l1_latency 28
-smem_latency 19
-gpgpu_flush_l1_cache 1
+-adpative_volta_cache_config 1
# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache
-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
@@ -87,7 +89,8 @@
# 128 KB Inst.
-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 64 KB Const
-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index d2a155c..39ed81c 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -591,6 +591,8 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info *
//Jin: launch latency management
m_launch_latency = g_kernel_launch_latency;
+
+ volta_cache_config_set=false;
}
kernel_info_t::~kernel_info_t()
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index e708fa7..6fa2ba0 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -301,6 +301,8 @@ public:
unsigned long long start_cycle;
unsigned long long end_cycle;
unsigned m_launch_latency;
+
+ mutable bool volta_cache_config_set;
};
struct core_config {
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index a11853a..8ae4702 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -29,7 +29,6 @@
#include "stat-tool.h"
#include <assert.h>
-#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
// used to allocate memory that is large enough to adapt the changes in cache size across kernels
const char * cache_request_status_str(enum cache_request_status status)
@@ -165,7 +164,7 @@ unsigned l2_cache_config::set_index(new_addr_type addr) const{
tag_array::~tag_array()
{
- unsigned cache_lines_num = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*m_config.get_num_lines();
+ unsigned cache_lines_num = m_config.get_max_num_lines();
for(unsigned i=0; i<cache_lines_num; ++i)
delete m_lines[i];
delete[] m_lines;
@@ -192,7 +191,7 @@ tag_array::tag_array( cache_config &config,
: m_config( config )
{
//assert( m_config.m_write_policy == READ_ONLY ); Old assert
- unsigned cache_lines_num = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER*config.get_num_lines();
+ unsigned cache_lines_num = config.get_max_num_lines();
m_lines = new cache_block_t*[cache_lines_num];
if(config.m_cache_type == NORMAL)
{
@@ -387,7 +386,7 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf)
//TODO: we need write back the flushed data to the upper level
void tag_array::flush()
{
- for (unsigned i=0; i < m_config.get_num_lines(); i++)
+ for (unsigned i=0; i < m_config.get_max_num_lines(); i++)
if(m_lines[i]->is_modified_line()) {
for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
@@ -396,7 +395,7 @@ void tag_array::flush()
void tag_array::invalidate()
{
- for (unsigned i=0; i < m_config.get_num_lines(); i++)
+ for (unsigned i=0; i < m_config.get_max_num_lines(); i++)
for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++)
m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ;
}
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4ed382c..9174d7f 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -38,6 +38,8 @@
#include "addrdec.h"
#include <iostream>
+#define MAX_DEFAULT_CACHE_SIZE_MULTIBLIER 4
+
enum cache_block_state {
INVALID=0,
RESERVED,
@@ -557,15 +559,15 @@ public:
}
if(m_alloc_policy == STREAMING) {
//For streaming cache, we set the alloc policy to be on-fill to remove all line_alloc_fail stalls
- //we set the MSHRs to be equal to the cache line. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
- // This is the easiest think we can think about to model (mimics) L1 streaming cache in Pascal and Volta
+ //we set the MSHRs to be equal to max allocated cache lines. This is possible by moving TAG to be shared between cache line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey associated with it)
+ //This is the easiest think we can think about to model (mimic) L1 streaming cache in Pascal and Volta
//Based on our microbenchmakrs, MSHRs entries have been increasing substantially in Pascal and Volta
//For more information about streaming cache, see:
// http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
// https://ieeexplore.ieee.org/document/8344474/
m_alloc_policy = ON_FILL;
- m_mshr_entries = m_nset*m_assoc;
+ m_mshr_entries = m_nset*m_assoc*MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;
if(m_cache_type == SECTOR)
m_mshr_entries *= SECTOR_CHUNCK_SIZE;
m_mshr_max_merge = MAX_WARP_PER_SM;
@@ -581,6 +583,7 @@ public:
m_nset_log2 = LOGB2(m_nset);
m_valid = true;
m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz;
+ original_m_assoc = m_assoc;
//For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies
//Read: Jouppi, Norman P. "Cache write policies and performance". ISCA 93.
@@ -646,7 +649,11 @@ public:
assert( m_valid );
return m_nset * m_assoc;
}
-
+ unsigned get_max_num_lines() const
+ {
+ assert( m_valid );
+ return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
+ }
void print( FILE *fp ) const
{
fprintf( fp, "Size = %d B (%d Set x %d-way x %d byte line)\n",
@@ -687,6 +694,21 @@ public:
{
return m_mshr_type;
}
+ void set_assoc(unsigned n)
+ {
+ //set new assoc. L1 cache dynamically resized in Volta
+ m_assoc = n;
+ }
+ unsigned get_nset() const
+ {
+ assert( m_valid );
+ return m_nset;
+ }
+ unsigned get_total_size_inKB() const
+ {
+ assert( m_valid );
+ return (m_assoc*m_nset*m_line_sz)/1024;
+ }
FuncCache get_cache_status() {return cache_status;}
char *m_config_string;
char *m_config_stringPrefL1;
@@ -708,6 +730,7 @@ protected:
unsigned m_nset_log2;
unsigned m_assoc;
unsigned m_atom_sz;
+ unsigned original_m_assoc;
enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO
enum write_policy_t m_write_policy; // 'T' = write through, 'B' = write back, 'R' = read only
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 08d4525..080cbac 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -307,6 +307,9 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
"Size of shared memory per shader core (default 16kB)",
"16384");
+ option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config,
+ "adpative_volta_cache_config",
+ "0");
option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault,
"Size of shared memory per shader core (default 16kB)",
"16384");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 0e2e1c2..2cc8a2e 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2744,6 +2744,35 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
abort();
}
+ if(adpative_volta_cache_config && !k.volta_cache_config_set) {
+ //For Volta, we assign the remaining shared memory to L1 cache
+ //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+ unsigned total_shmed = kernel_info->smem * result;
+ assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
+ assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+ assert(m_L1D_config.get_nset() == 4); //Volta L1 has four sets
+ if(total_shmed < gpgpu_shmem_size){
+ if(total_shmed == 0)
+ m_L1D_config.set_assoc(256); //L1 is 128KB ans shd=0
+ else if(total_shmed > 0 && total_shmed <= 8192)
+ m_L1D_config.set_assoc(240); //L1 is 120KB ans shd=8KB
+ else if(total_shmed > 8192 && total_shmed <= 16384)
+ m_L1D_config.set_assoc(224); //L1 is 112KB ans shd=16KB
+ else if(total_shmed > 16384 && total_shmed <= 32768)
+ m_L1D_config.set_assoc(192); //L1 is 96KB ans shd=32KB
+ else if(total_shmed > 32768 && total_shmed <= 65536)
+ m_L1D_config.set_assoc(128); //L1 is 64KB ans shd=64KB
+ else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+ m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB
+ else
+ assert(0);
+
+ printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB());
+ }
+
+ k.volta_cache_config_set = true;
+ }
+
return result;
}
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index e07096e..92b4159 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1409,6 +1409,8 @@ struct shader_core_config : public core_config
//Jin: concurrent kernel on sm
bool gpgpu_concurrent_kernel_sm;
+
+ bool adpative_volta_cache_config;
};
struct shader_core_stats_pod {
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 00:34:07 +0000