diff options
| -rw-r--r-- | src/cuda-sim/ptx.y | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 3 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 10 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.h | 3 |
4 files changed, 15 insertions, 2 deletions
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index ec058f6..f0b67fb 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -357,6 +357,7 @@ instruction_statement: instruction SEMI_COLON instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN | opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN | opcode_spec operand_list | opcode_spec ; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3200c9c..bd77c7b 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -236,6 +236,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp, "Max number of instructions that can be issued per warp in one cycle by scheduler", "2"); + option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, + "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 742d3c9..060dd07 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2046,13 +2046,19 @@ simt_core_cluster::simt_core_cluster( class gpgpu_sim *gpu, for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ ) { unsigned sid = m_config->cid_to_sid(i,m_cluster_id); m_core[i] = new shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats); + m_core_sim_order.push_back(i); } } void simt_core_cluster::core_cycle() { - for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) - m_core[i]->cycle(); + for( std::list<unsigned>::iterator it = m_core_sim_order.begin(); it != m_core_sim_order.end(); ++it ) { + m_core[*it]->cycle(); + } + + if (m_config->simt_core_sim_order == 1) { + m_core_sim_order.splice(m_core_sim_order.end(), m_core_sim_order, m_core_sim_order.begin()); + } } void simt_core_cluster::reinit() diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1d86f02..759a58b 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -985,6 +985,8 @@ struct shader_core_config : public core_config unsigned n_simt_clusters; unsigned n_simt_ejection_buffer_size; unsigned ldst_unit_response_queue_size; + + int simt_core_sim_order; unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; } }; @@ -1275,6 +1277,7 @@ private: shader_core_ctx **m_core; unsigned m_cta_issue_next_core; + std::list<unsigned> m_core_sim_order; std::list<mem_fetch*> m_response_fifo; }; |