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-rw-r--r--src/gpgpu-sim/gpu-sim.cc7
-rw-r--r--src/gpgpu-sim/gpu-sim.h1
-rw-r--r--src/gpgpu-sim/l2cache.cc77
-rw-r--r--src/gpgpu-sim/l2cache.h1
4 files changed, 76 insertions, 10 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 343ff86..92d5366 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -156,6 +156,8 @@ void memory_config::reg_options(class OptionParser * opp)
{
option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy,
"Fill the L2 cache on memcpy", "1");
+ option_parser_register(opp, "-simple_dram_model", OPT_BOOL, &simple_dram_model,
+ "simple_dram_model with fixed latency and BW", "0");
option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type,
"0 = fifo, 1 = FR-FCFS (defaul)", "1");
option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config,
@@ -1606,7 +1608,10 @@ void gpgpu_sim::cycle()
if (clock_mask & DRAM) {
for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
- m_memory_partition_unit[i]->dram_cycle(); // Issue the dram command (scheduler + delay model)
+ if(m_memory_config->simple_dram_model)
+ m_memory_partition_unit[i]->simple_dram_model_cycle();
+ else
+ m_memory_partition_unit[i]->dram_cycle(); // Issue the dram command (scheduler + delay model)
// Update performance counters for DRAM
m_memory_partition_unit[i]->set_dram_power_stats(m_power_stats->pwr_mem_stat->n_cmd[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_activity[CURRENT_STAT_IDX][i],
m_power_stats->pwr_mem_stat->n_nop[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_act[CURRENT_STAT_IDX][i], m_power_stats->pwr_mem_stat->n_pre[CURRENT_STAT_IDX][i],
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index e98e499..c14d0a7 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -290,6 +290,7 @@ struct memory_config {
unsigned write_high_watermark;
unsigned write_low_watermark;
bool m_perf_sim_memcpy;
+ bool simple_dram_model;
};
// global counters and flags (please try not to add to this list!!!)
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index 0edc3b7..f24a596 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -203,7 +203,67 @@ int memory_partition_unit::global_sub_partition_id_to_local_id(int global_sub_pa
return (global_sub_partition_id - m_id * m_config->m_n_sub_partition_per_memory_channel);
}
-void memory_partition_unit::dram_cycle()
+void memory_partition_unit::simple_dram_model_cycle()
+{
+
+ // pop completed memory request from dram and push it to dram-to-L2 queue
+ // of the original sub partition
+ if (!m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle )) {
+ mem_fetch* mf_return = m_dram_latency_queue.front().req;
+ if( mf_return->get_access_type() != L1_WRBK_ACC && mf_return->get_access_type() != L2_WRBK_ACC ) {
+ mf_return->set_reply();
+
+ unsigned dest_global_spid = mf_return->get_sub_partition_id();
+ int dest_spid = global_sub_partition_id_to_local_id(dest_global_spid);
+ assert(m_sub_partition[dest_spid]->get_id() == dest_global_spid);
+ if (!m_sub_partition[dest_spid]->dram_L2_queue_full()) {
+ if( mf_return->get_access_type() == L1_WRBK_ACC ) {
+ m_sub_partition[dest_spid]->set_done(mf_return);
+ delete mf_return;
+ } else {
+ m_sub_partition[dest_spid]->dram_L2_queue_push(mf_return);
+ mf_return->set_status(IN_PARTITION_DRAM_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+ m_arbitration_metadata.return_credit(dest_spid);
+ MEMPART_DPRINTF("mem_fetch request %p return from dram to sub partition %d\n", mf_return, dest_spid);
+ }
+ m_dram_latency_queue.pop_front();
+ }
+
+ } else {
+ this->set_done(mf_return);
+ delete mf_return;
+ m_dram_latency_queue.pop_front();
+ }
+ }
+
+ // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top();
+ //if( !m_dram->full(mf->is_write()) ) {
+ // L2->DRAM queue to DRAM latency queue
+ // Arbitrate among multiple L2 subpartitions
+ int last_issued_partition = m_arbitration_metadata.last_borrower();
+ for (unsigned p = 0; p < m_config->m_n_sub_partition_per_memory_channel; p++) {
+ int spid = (p + last_issued_partition + 1) % m_config->m_n_sub_partition_per_memory_channel;
+ if (!m_sub_partition[spid]->L2_dram_queue_empty() && can_issue_to_dram(spid)) {
+ mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top();
+ if(m_dram->full(mf->is_write()) )
+ break;
+
+ m_sub_partition[spid]->L2_dram_queue_pop();
+ MEMPART_DPRINTF("Issue mem_fetch request %p from sub partition %d to dram\n", mf, spid);
+ dram_delay_t d;
+ d.req = mf;
+ d.ready_cycle = gpu_sim_cycle+gpu_tot_sim_cycle + m_config->dram_latency;
+ m_dram_latency_queue.push_back(d);
+ mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+ m_arbitration_metadata.borrow_credit(spid);
+ break; // the DRAM should only accept one request per cycle
+ }
+ }
+ //}
+
+}
+
+void memory_partition_unit::dram_cycle()
{
// pop completed memory request from dram and push it to dram-to-L2 queue
// of the original sub partition
@@ -228,8 +288,8 @@ void memory_partition_unit::dram_cycle()
m_dram->return_queue_pop();
}
- m_dram->cycle();
- m_dram->dram_log(SAMPLELOG);
+ m_dram->cycle();
+ m_dram->dram_log(SAMPLELOG);
// mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top();
//if( !m_dram->full(mf->is_write()) ) {
@@ -257,12 +317,11 @@ void memory_partition_unit::dram_cycle()
//}
// DRAM latency queue
-
- if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) {
- mem_fetch* mf = m_dram_latency_queue.front().req;
- m_dram_latency_queue.pop_front();
- m_dram->push(mf);
- }
+ if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) {
+ mem_fetch* mf = m_dram_latency_queue.front().req;
+ m_dram_latency_queue.pop_front();
+ m_dram->push(mf);
+ }
}
void memory_partition_unit::set_done( mem_fetch *mf )
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index beafdd3..9a51c0e 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -65,6 +65,7 @@ public:
void cache_cycle( unsigned cycle );
void dram_cycle();
+ void simple_dram_model_cycle();
void set_done( mem_fetch *mf );
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:25:51 +0000