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-rw-r--r--src/abstract_hardware_model.h16
-rw-r--r--src/gpgpu-sim/shader.cc72
-rw-r--r--src/gpgpu-sim/shader.h26
3 files changed, 74 insertions, 40 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index d70c3eb..90ae448 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1316,6 +1316,12 @@ class register_set {
}
return false;
}
+ bool has_ready(bool sub_core_model, unsigned reg_id) {
+ if (!sub_core_model) return has_ready();
+ assert(reg_id < regs.size());
+ return (not regs[reg_id]->empty())
+ }
+
unsigned get_ready_reg_id() {
// for sub core model we need to figure which reg_id has the ready warp
// this function should only be called if has_ready() was true
@@ -1376,6 +1382,16 @@ class register_set {
}
return ready;
}
+ warp_inst_t **get_ready(bool sub_core_model, unsigned reg_id) {
+ if (!sub_core_model)
+ return get_ready();
+ warp_inst_t **ready;
+ ready = NULL;
+ assert(reg_id < regs.size());
+ if (not regs[reg_id]->empty)
+ ready = &regs[reg_id];
+ return ready;
+ }
void print(FILE *fp) const {
fprintf(fp, "%s : @%p\n", m_name, this);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index e3a3e9c..ca421de 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -377,41 +377,41 @@ void shader_core_ctx::create_exec_pipeline() {
// m_fu = new simd_function_unit*[m_num_function_units];
- for (int k = 0; k < m_config->gpgpu_num_sp_units; k++) {
- m_fu.push_back(new sp_unit(&m_pipeline_reg[EX_WB], m_config, this));
+ for (unsigned k = 0; k < m_config->gpgpu_num_sp_units; k++) {
+ m_fu.push_back(new sp_unit(&m_pipeline_reg[EX_WB], m_config, this, k));
m_dispatch_port.push_back(ID_OC_SP);
m_issue_port.push_back(OC_EX_SP);
}
- for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) {
- m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this));
+ for (unsigned k = 0; k < m_config->gpgpu_num_dp_units; k++) {
+ m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this, k));
m_dispatch_port.push_back(ID_OC_DP);
m_issue_port.push_back(OC_EX_DP);
}
- for (int k = 0; k < m_config->gpgpu_num_int_units; k++) {
- m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this));
+ for (unsigned k = 0; k < m_config->gpgpu_num_int_units; k++) {
+ m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this, k));
m_dispatch_port.push_back(ID_OC_INT);
m_issue_port.push_back(OC_EX_INT);
}
- for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
- m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this));
+ for (unsigned k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
+ m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this, k));
m_dispatch_port.push_back(ID_OC_SFU);
m_issue_port.push_back(OC_EX_SFU);
}
- for (int k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) {
- m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this));
+ for (unsigned k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) {
+ m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this, k));
m_dispatch_port.push_back(ID_OC_TENSOR_CORE);
m_issue_port.push_back(OC_EX_TENSOR_CORE);
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
for (unsigned k = 0; k < m_config->m_specialized_unit[j].num_units; k++) {
m_fu.push_back(new specialized_unit(
&m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j,
m_config->m_specialized_unit[j].name,
- m_config->m_specialized_unit[j].latency));
+ m_config->m_specialized_unit[j].latency, k));
m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID);
m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID);
}
@@ -419,7 +419,7 @@ void shader_core_ctx::create_exec_pipeline() {
m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this,
&m_operand_collector, m_scoreboard, m_config,
- m_memory_config, m_stats, m_sid, m_tpc);
+ m_memory_config, m_stats, m_sid, m_tpc, static_cast<unsigned>(0));
m_fu.push_back(m_ldst_unit);
m_dispatch_port.push_back(ID_OC_MEM);
m_issue_port.push_back(OC_EX_MEM);
@@ -1669,8 +1669,13 @@ void shader_core_ctx::execute() {
m_fu[n]->active_lanes_in_pipeline();
unsigned issue_port = m_issue_port[n];
register_set &issue_inst = m_pipeline_reg[issue_port];
- warp_inst_t **ready_reg = issue_inst.get_ready();
- if (issue_inst.has_ready() && m_fu[n]->can_issue(**ready_reg)) {
+ unsigned reg_id;
+ bool partition_issue = m_config->sub_core_model && m_fu[n]->is_issue_partitioned();
+ if (m_config->sub_core_model) {
+ reg_id = m_fu[n]->get_issue_reg_id();
+ }
+ warp_inst_t **ready_reg = issue_inst.get_ready(partition_issue, reg_id);
+ if (issue_inst.has_ready(partition_issue, reg_id) && m_fu[n]->can_issue(**ready_reg)) {
bool schedule_wb_now = !m_fu[n]->stallable();
int resbus = -1;
if (schedule_wb_now &&
@@ -2113,16 +2118,17 @@ simd_function_unit::simd_function_unit(const shader_core_config *config) {
}
sfu::sfu(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core)
- : pipelined_simd_unit(result_port, config, config->max_sfu_latency, core) {
+ shader_core_ctx *core, unsigned issue_reg_id)
+ : pipelined_simd_unit(result_port, config, config->max_sfu_latency, core,
+ issue_reg_id) {
m_name = "SFU";
}
tensor_core::tensor_core(register_set *result_port,
const shader_core_config *config,
- shader_core_ctx *core)
+ shader_core_ctx *core, unsigned issue_reg_id)
: pipelined_simd_unit(result_port, config, config->max_tensor_core_latency,
- core) {
+ core, issue_reg_id) {
m_name = "TENSOR_CORE";
}
@@ -2208,29 +2214,29 @@ void tensor_core::active_lanes_in_pipeline() {
}
sp_unit::sp_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core)
- : pipelined_simd_unit(result_port, config, config->max_sp_latency, core) {
+ shader_core_ctx *core, unsigned issue_reg_id)
+ : pipelined_simd_unit(result_port, config, config->max_sp_latency, core, issue_reg_id) {
m_name = "SP ";
}
specialized_unit::specialized_unit(register_set *result_port,
const shader_core_config *config,
shader_core_ctx *core, unsigned supported_op,
- char *unit_name, unsigned latency)
- : pipelined_simd_unit(result_port, config, latency, core) {
+ char *unit_name, unsigned latency, unsigned issue_reg_id)
+ : pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) {
m_name = unit_name;
m_supported_op = supported_op;
}
dp_unit::dp_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core)
- : pipelined_simd_unit(result_port, config, config->max_dp_latency, core) {
+ shader_core_ctx *core, unsigned issue_reg_id)
+ : pipelined_simd_unit(result_port, config, config->max_dp_latency, core, issue_reg_id) {
m_name = "DP ";
}
int_unit::int_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core)
- : pipelined_simd_unit(result_port, config, config->max_int_latency, core) {
+ shader_core_ctx *core, unsigned issue_reg_id)
+ : pipelined_simd_unit(result_port, config, config->max_int_latency, core, issue_reg_id) {
m_name = "INT ";
}
@@ -2269,7 +2275,8 @@ void int_unit ::issue(register_set &source_reg) {
pipelined_simd_unit::pipelined_simd_unit(register_set *result_port,
const shader_core_config *config,
unsigned max_latency,
- shader_core_ctx *core)
+ shader_core_ctx *core,
+ unsigned issue_reg_id)
: simd_function_unit(config) {
m_result_port = result_port;
m_pipeline_depth = max_latency;
@@ -2277,6 +2284,7 @@ pipelined_simd_unit::pipelined_simd_unit(register_set *result_port,
for (unsigned i = 0; i < m_pipeline_depth; i++)
m_pipeline_reg[i] = new warp_inst_t(config);
m_core = core;
+ m_issue_reg_id = issue_reg_id;
active_insts_in_pipeline = 0;
}
@@ -2359,8 +2367,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt,
shader_core_ctx *core, opndcoll_rfu_t *operand_collector,
Scoreboard *scoreboard, const shader_core_config *config,
const memory_config *mem_config, shader_core_stats *stats,
- unsigned sid, unsigned tpc)
- : pipelined_simd_unit(NULL, config, config->smem_latency, core),
+ unsigned sid, unsigned tpc, unsigned issue_reg_id)
+ : pipelined_simd_unit(NULL, config, config->smem_latency, core, issue_reg_id),
m_next_wb(config) {
assert(config->smem_latency > 1);
init(icnt, mf_allocator, core, operand_collector, scoreboard, config,
@@ -2387,8 +2395,8 @@ ldst_unit::ldst_unit(mem_fetch_interface *icnt,
shader_core_ctx *core, opndcoll_rfu_t *operand_collector,
Scoreboard *scoreboard, const shader_core_config *config,
const memory_config *mem_config, shader_core_stats *stats,
- unsigned sid, unsigned tpc, l1_cache *new_l1d_cache)
- : pipelined_simd_unit(NULL, config, 3, core),
+ unsigned sid, unsigned tpc, l1_cache *new_l1d_cache, unsigned issue_reg_id)
+ : pipelined_simd_unit(NULL, config, 3, core, issue_reg_id),
m_L1D(new_l1d_cache),
m_next_wb(config) {
init(icnt, mf_allocator, core, operand_collector, scoreboard, config,
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 00e7deb..ba37b0c 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1075,7 +1075,7 @@ class pipelined_simd_unit : public simd_function_unit {
public:
pipelined_simd_unit(register_set *result_port,
const shader_core_config *config, unsigned max_latency,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
// modifiers
virtual void cycle();
@@ -1096,6 +1096,7 @@ class pipelined_simd_unit : public simd_function_unit {
virtual bool can_issue(const warp_inst_t &inst) const {
return simd_function_unit::can_issue(inst);
}
+ unsigned get_issue_reg_id() { return m_issue_reg_id; }
virtual void print(FILE *fp) const {
simd_function_unit::print(fp);
for (int s = m_pipeline_depth - 1; s >= 0; s--) {
@@ -1111,6 +1112,8 @@ class pipelined_simd_unit : public simd_function_unit {
warp_inst_t **m_pipeline_reg;
register_set *m_result_port;
class shader_core_ctx *m_core;
+ unsigned m_issue_reg_id; // if sub_core_model is enabled we can only issue from a
+ // subset of operand collectors
unsigned active_insts_in_pipeline;
};
@@ -1118,7 +1121,7 @@ class pipelined_simd_unit : public simd_function_unit {
class sfu : public pipelined_simd_unit {
public:
sfu(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
switch (inst.op) {
case SFU_OP:
@@ -1134,12 +1137,13 @@ class sfu : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return true; }
};
class dp_unit : public pipelined_simd_unit {
public:
dp_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
switch (inst.op) {
case DP_OP:
@@ -1151,12 +1155,13 @@ class dp_unit : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return true; }
};
class tensor_core : public pipelined_simd_unit {
public:
tensor_core(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
switch (inst.op) {
case TENSOR_CORE_OP:
@@ -1168,12 +1173,13 @@ class tensor_core : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return true; }
};
class int_unit : public pipelined_simd_unit {
public:
int_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
switch (inst.op) {
case SFU_OP:
@@ -1199,12 +1205,13 @@ class int_unit : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return true; }
};
class sp_unit : public pipelined_simd_unit {
public:
sp_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core);
+ shader_core_ctx *core, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
switch (inst.op) {
case SFU_OP:
@@ -1228,13 +1235,14 @@ class sp_unit : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return true; }
};
class specialized_unit : public pipelined_simd_unit {
public:
specialized_unit(register_set *result_port, const shader_core_config *config,
shader_core_ctx *core, unsigned supported_op,
- char *unit_name, unsigned latency);
+ char *unit_name, unsigned latency, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
if (inst.op != m_supported_op) {
return false;
@@ -1243,6 +1251,7 @@ class specialized_unit : public pipelined_simd_unit {
}
virtual void active_lanes_in_pipeline();
virtual void issue(register_set &source_reg);
+ bool is_issue_partitioned() { return false; }
private:
unsigned m_supported_op;
@@ -1260,10 +1269,11 @@ class ldst_unit : public pipelined_simd_unit {
shader_core_ctx *core, opndcoll_rfu_t *operand_collector,
Scoreboard *scoreboard, const shader_core_config *config,
const memory_config *mem_config, class shader_core_stats *stats,
- unsigned sid, unsigned tpc);
+ unsigned sid, unsigned tpc, unsigned issue_reg_id);
// modifiers
virtual void issue(register_set &inst);
+ bool is_issue_partitioned() { return false; }
virtual void cycle();
void fill(mem_fetch *mf);
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:33:02 +0000