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-rw-r--r--configs/tested-cfgs/SM75_RTX2060/gpgpusim.config19
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config21
-rw-r--r--configs/tested-cfgs/SM7_TITANV/gpgpusim.config19
-rw-r--r--configs/tested-cfgs/SM86_RTX3070/gpgpusim.config15
-rw-r--r--src/abstract_hardware_model.h1
-rw-r--r--src/gpgpu-sim/gpu-cache.h59
-rw-r--r--src/gpgpu-sim/shader.cc47
-rw-r--r--src/gpgpu-sim/shader.h26
8 files changed, 103 insertions, 104 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index d7573ab..f715f3a 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -99,19 +99,22 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_adaptive_cache_config 0
--gpgpu_shmem_option 0,8,16,32,64,100
--gpgpu_unified_l1d_size 128
+-gpgpu_adaptive_cache_config 1
+-gpgpu_shmem_option 32,64
+-gpgpu_unified_l1d_size 96
+# L1 cache configuration
-gpgpu_l1_banks 4
--gpgpu_cache:dl1 S:1:128:512,L:L:m:N:L,A:512:8,16:0,32
+-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
+-gpgpu_l1_cache_write_ratio 25
+-gpgpu_l1_latency 20
+-gpgpu_gmem_skip_L1D 0
+-gpgpu_n_cluster_ejection_buffer_size 32
+-gpgpu_flush_l1_cache 1
+# shared memory configuration
-gpgpu_shmem_size 65536
-gpgpu_shmem_sizeDefault 65536
-gpgpu_shmem_per_block 65536
--gpgpu_gmem_skip_L1D 0
--gpgpu_n_cluster_ejection_buffer_size 32
--gpgpu_l1_latency 20
-gpgpu_smem_latency 20
--gpgpu_flush_l1_cache 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache
-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 59c7f43..5f22a42 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -94,7 +94,7 @@
-gpgpu_shmem_num_banks 32
-gpgpu_shmem_limited_broadcast 0
-gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
+-gpgpu_coalesce_arch 70
# Volta has four schedulers per core
-gpgpu_num_sched_per_core 4
@@ -113,20 +113,21 @@
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
# disable this mode in case of multi kernels/apps execution
-gpgpu_adaptive_cache_config 1
-# Volta unified cache has four banks
+-gpgpu_shmem_option 0,8,16,32,64,96
+-gpgpu_unified_l1d_size 128
+# L1 cache configuration
-gpgpu_l1_banks 4
--gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32
+-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
+-gpgpu_l1_cache_write_ratio 25
+-gpgpu_l1_latency 20
+-gpgpu_gmem_skip_L1D 0
+-gpgpu_flush_l1_cache 1
+-gpgpu_n_cluster_ejection_buffer_size 32
+# shared memory configuration
-gpgpu_shmem_size 98304
-gpgpu_shmem_sizeDefault 98304
-gpgpu_shmem_per_block 65536
--gpgpu_gmem_skip_L1D 0
--gpgpu_n_cluster_ejection_buffer_size 32
--gpgpu_l1_latency 20
-gpgpu_smem_latency 20
--gpgpu_flush_l1_cache 1
--gpgpu_l1_cache_write_ratio 25
--gpgpu_shmem_option 0,12,24,48,96
--gpgpu_unified_l1d_size 128
# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache
-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 32245d7..c44563f 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -114,20 +114,21 @@
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
# disable this mode in case of multi kernels/apps execution
-gpgpu_adaptive_cache_config 1
-# Volta unified cache has four banks
+-gpgpu_shmem_option 0,8,16,32,64,96
+-gpgpu_unified_l1d_size 128
+# L1 cache configuration
-gpgpu_l1_banks 4
--gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32
+-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
+-gpgpu_l1_cache_write_ratio 25
+-gpgpu_gmem_skip_L1D 0
+-gpgpu_l1_latency 20
+-gpgpu_flush_l1_cache 1
+-gpgpu_n_cluster_ejection_buffer_size 32
+# shared memory configuration
-gpgpu_shmem_size 98304
-gpgpu_shmem_sizeDefault 98304
-gpgpu_shmem_per_block 65536
--gpgpu_gmem_skip_L1D 0
--gpgpu_n_cluster_ejection_buffer_size 32
--gpgpu_l1_latency 20
-gpgpu_smem_latency 20
--gpgpu_flush_l1_cache 1
--gpgpu_l1_cache_write_ratio 25
--gpgpu_shmem_option 0,12,24,48,96
--gpgpu_unified_l1d_size 128
# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32
diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
index f5418ad..02cdb9e 100644
--- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
+++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
@@ -101,23 +101,26 @@
## L1/shared memory configuration
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Default config is 28KB DL1 and 100KB shared memory
# In Ampere, we assign the remaining shared memory to L1 cache
# if the assigned shd mem = 0, then L1 cache = 128KB
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#global-memory-8-x
# disable this mode in case of multi kernels/apps execution
-gpgpu_adaptive_cache_config 1
+-gpgpu_shmem_option 0,8,16,32,64,100
+-gpgpu_unified_l1d_size 128
# Ampere unified cache has four banks
-gpgpu_l1_banks 4
--gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32
+-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
+-gpgpu_l1_cache_write_ratio 25
+-gpgpu_gmem_skip_L1D 0
+-gpgpu_l1_latency 20
+-gpgpu_n_cluster_ejection_buffer_size 32
+-gpgpu_flush_l1_cache 1
+# shared memory configuration
-gpgpu_shmem_size 102400
-gpgpu_shmem_sizeDefault 102400
-gpgpu_shmem_per_block 102400
--gpgpu_gmem_skip_L1D 0
--gpgpu_n_cluster_ejection_buffer_size 32
--gpgpu_l1_latency 20
-gpgpu_smem_latency 20
--gpgpu_flush_l1_cache 1
# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 3MB L2 cache
-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 17a1cec..b33c50b 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -374,6 +374,7 @@ class core_config {
unsigned mem_warp_parts;
mutable unsigned gpgpu_shmem_size;
char *gpgpu_shmem_option;
+ std::vector<unsigned> shmem_opt_list;
unsigned gpgpu_shmem_sizeDefault;
unsigned gpgpu_shmem_sizePrefL1;
unsigned gpgpu_shmem_sizePrefShared;
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index d801528..6698d92 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -210,13 +210,13 @@ struct line_cache_block : public cache_block_t {
m_status = status;
}
virtual void set_byte_mask(mem_fetch *mf) {
- m_byte_mask = m_byte_mask | mf->get_access_byte_mask();
+ m_dirty_byte_mask = m_dirty_byte_mask | mf->get_access_byte_mask();
}
virtual void set_byte_mask(mem_access_byte_mask_t byte_mask) {
- m_byte_mask = m_byte_mask | byte_mask;
+ m_dirty_byte_mask = m_dirty_byte_mask | byte_mask;
}
virtual mem_access_byte_mask_t get_dirty_byte_mask() {
- return m_byte_mask;
+ return m_dirty_byte_mask;
}
virtual mem_access_sector_mask_t get_dirty_sector_mask() {
mem_access_sector_mask_t sector_mask;
@@ -270,7 +270,7 @@ struct line_cache_block : public cache_block_t {
bool m_set_readable_on_fill;
bool m_set_byte_mask_on_fill;
bool m_readable;
- mem_access_byte_mask_t m_byte_mask;
+ mem_access_byte_mask_t m_dirty_byte_mask;
};
struct sector_cache_block : public cache_block_t {
@@ -290,7 +290,7 @@ struct sector_cache_block : public cache_block_t {
m_line_alloc_time = 0;
m_line_last_access_time = 0;
m_line_fill_time = 0;
- m_byte_mask.reset();
+ m_dirty_byte_mask.reset();
}
virtual void allocate(new_addr_type tag, new_addr_type block_addr,
@@ -405,13 +405,13 @@ struct sector_cache_block : public cache_block_t {
}
virtual void set_byte_mask(mem_fetch *mf) {
- m_byte_mask = m_byte_mask | mf->get_access_byte_mask();
+ m_dirty_byte_mask = m_dirty_byte_mask | mf->get_access_byte_mask();
}
virtual void set_byte_mask(mem_access_byte_mask_t byte_mask) {
- m_byte_mask = m_byte_mask | byte_mask;
+ m_dirty_byte_mask = m_dirty_byte_mask | byte_mask;
}
virtual mem_access_byte_mask_t get_dirty_byte_mask() {
- return m_byte_mask;
+ return m_dirty_byte_mask;
}
virtual mem_access_sector_mask_t get_dirty_sector_mask() {
mem_access_sector_mask_t sector_mask;
@@ -492,7 +492,7 @@ struct sector_cache_block : public cache_block_t {
bool m_set_readable_on_fill[SECTOR_CHUNCK_SIZE];
bool m_set_byte_mask_on_fill;
bool m_readable[SECTOR_CHUNCK_SIZE];
- mem_access_byte_mask_t m_byte_mask;
+ mem_access_byte_mask_t m_dirty_byte_mask;
unsigned get_sector_index(mem_access_sector_mask_t sector_mask) {
assert(sector_mask.count() == 1);
@@ -575,14 +575,6 @@ class cache_config {
}
exit_parse_error();
}
-
- // set * assoc * cacheline size. Then convert Byte to KB
- unsigned original_size = m_nset * m_assoc * m_line_sz / 1024;
- if (m_unified_cache_size > 0) {
- max_cache_multiplier = m_unified_cache_size / original_size;
- } else {
- max_cache_multiplier = MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;
- }
switch (ct) {
case 'N':
@@ -604,16 +596,6 @@ class cache_config {
default:
exit_parse_error();
}
- switch (rp) {
- case 'L':
- m_replacement_policy = LRU;
- break;
- case 'F':
- m_replacement_policy = FIFO;
- break;
- default:
- exit_parse_error();
- }
switch (wp) {
case 'R':
m_write_policy = READ_ONLY;
@@ -693,7 +675,6 @@ class cache_config {
m_sector_sz_log2 = LOGB2(SECTOR_SIZE);
original_m_assoc = m_assoc;
-
// For more details about difference between FETCH_ON_WRITE and WRITE
// VALIDAE policies Read: Jouppi, Norman P. "Cache write policies and
// performance". ISCA 93. WRITE_ALLOCATE is the old write policy in
@@ -785,13 +766,11 @@ class cache_config {
}
unsigned get_max_num_lines() const {
assert(m_valid);
- // gpgpu_unified_cache_size is in KB while original_sz is in B
- return max_cache_multiplier * m_nset * original_m_assoc;
+ return get_max_cache_multiplier() * m_nset * original_m_assoc;
}
unsigned get_max_assoc() const {
assert(m_valid);
- // gpgpu_unified_cache_size is in KB while original_sz is in B
- return max_cache_multiplier * original_m_assoc;
+ return get_max_cache_multiplier() * original_m_assoc;
}
void print(FILE *fp) const {
fprintf(fp, "Size = %d B (%d Set x %d-way x %d byte line)\n",
@@ -800,6 +779,8 @@ class cache_config {
virtual unsigned set_index(new_addr_type addr) const;
+ virtual unsigned get_max_cache_multiplier() const { return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;}
+
unsigned hash_function(new_addr_type addr, unsigned m_nset,
unsigned m_line_sz_log2, unsigned m_nset_log2,
unsigned m_index_function) const;
@@ -841,7 +822,6 @@ class cache_config {
char *m_config_stringPrefL1;
char *m_config_stringPrefShared;
FuncCache cache_status;
- unsigned m_unified_cache_size;
unsigned m_wr_percent;
write_allocate_policy_t get_write_allocate_policy() {
return m_write_alloc_policy;
@@ -868,7 +848,6 @@ class cache_config {
unsigned m_sector_sz_log2;
unsigned original_m_assoc;
bool m_is_streaming;
- unsigned max_cache_multiplier;
enum replacement_policy_t m_replacement_policy; // 'L' = LRU, 'F' = FIFO
enum write_policy_t
@@ -923,6 +902,18 @@ class l1d_cache_config : public cache_config {
unsigned l1_banks_byte_interleaving;
unsigned l1_banks_byte_interleaving_log2;
unsigned l1_banks_hashing_function;
+ unsigned m_unified_cache_size;
+ virtual unsigned get_max_cache_multiplier() const {
+ // set * assoc * cacheline size. Then convert Byte to KB
+ // gpgpu_unified_cache_size is in KB while original_sz is in B
+ if (m_unified_cache_size > 0) {
+ unsigned original_size = m_nset * original_m_assoc * m_line_sz / 1024;
+ assert(m_unified_cache_size % original_size == 0);
+ return m_unified_cache_size / original_size;
+ } else {
+ return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER;
+ }
+ }
};
class l2_cache_config : public cache_config {
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 75fbe16..7f27b7b 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3334,56 +3334,29 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const {
if (adaptive_cache_config && !k.cache_config_set) {
// For more info about adaptive cache, see
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
- std::vector<unsigned> shmem_list;
- for (unsigned i = 0; i < strlen(gpgpu_shmem_option); i++) {
- char option[4];
- int j = 0;
- while (gpgpu_shmem_option[i] != ',' && i < strlen(gpgpu_shmem_option)) {
- if (gpgpu_shmem_option[i] == ' ') {
- // skip spaces
- i++;
- } else {
- if (!isdigit(gpgpu_shmem_option[i])) {
- // check for non digits, which should not be here
- assert(0 && "invalid config: -gpgpu_shmem_option");
- }
- option[j] = gpgpu_shmem_option[i];
- j++;
- i++;
- }
- }
- // convert KB -> B
- shmem_list.push_back((unsigned)atoi(option) * 1024);
- }
-
unsigned total_shmem = kernel_info->smem * result;
+ assert(total_shmem >= 0 && total_shmem <= shmem_opt_list.back());
+
// Unified cache config is in KB. Converting to B
unsigned total_unified = m_L1D_config.m_unified_cache_size * 1024;
- std::sort(shmem_list.begin(), shmem_list.end());
- assert(total_shmem >= 0 && total_shmem <= shmem_list.back());
switch (adaptive_cache_config) {
case FIXED:
break;
case ADAPTIVE_CACHE: {
- // For more info about adaptive cache, see
bool l1d_configured = false;
unsigned max_assoc = m_L1D_config.get_max_assoc();
- if (total_shmem == 0) {
- m_L1D_config.set_assoc(max_assoc);
- l1d_configured = true;
- } else {
- for (std::vector<unsigned>::iterator it = shmem_list.begin();
- it < shmem_list.end() - 1; it++) {
- if (total_shmem > *it && total_shmem <= *(it + 1)) {
- float l1_ratio = 1 - (float) *(it + 1) / total_unified;
- m_L1D_config.set_assoc(max_assoc * l1_ratio);
- l1d_configured = true;
- break;
- }
+ for (std::vector<unsigned>::const_iterator it = shmem_opt_list.begin();
+ it < shmem_opt_list.end(); it++) {
+ if (total_shmem <= *it) {
+ float l1_ratio = 1 - ((float) *(it) / total_unified);
+ m_L1D_config.set_assoc(max_assoc * l1_ratio);
+ l1d_configured = true;
+ break;
}
}
+
assert(l1d_configured && "no shared memory option found");
break;
}
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index a7a2c02..42bbdcb 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1495,6 +1495,32 @@ class shader_core_config : public core_config {
} else
break; // we only accept continuous specialized_units, i.e., 1,2,3,4
}
+
+ //parse gpgpu_shmem_option for adpative cache config
+ if(adaptive_cache_config) {
+ for (unsigned i = 0; i < strlen(gpgpu_shmem_option); i++) {
+ char option[4];
+ int j = 0;
+ while (gpgpu_shmem_option[i] != ',' && i < strlen(gpgpu_shmem_option)) {
+ if (gpgpu_shmem_option[i] == ' ') {
+ // skip spaces
+ i++;
+ } else {
+ if (!isdigit(gpgpu_shmem_option[i])) {
+ // check for non digits, which should not be here
+ assert(0 && "invalid config: -gpgpu_shmem_option");
+ }
+ option[j] = gpgpu_shmem_option[i];
+ j++;
+ i++;
+ }
+ }
+ // convert KB -> B
+ shmem_opt_list.push_back((unsigned)atoi(option) * 1024);
+ }
+ std::sort(shmem_opt_list.begin(), shmem_opt_list.end());
+ }
+
}
void reg_options(class OptionParser *opp);
unsigned max_cta(const kernel_info_t &k) const;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 01:23:36 +0000