diff options
| -rw-r--r-- | CHANGES | 6 | ||||
| -rw-r--r-- | configs/GTX480/config_fermi_islip.icnt | 2 | ||||
| -rw-r--r-- | configs/GTX480/gpgpusim.config | 9 | ||||
| -rw-r--r-- | configs/TeslaC2050/config_fermi_islip.icnt | 2 | ||||
| -rw-r--r-- | configs/TeslaC2050/gpgpusim.config | 9 |
5 files changed, 18 insertions, 10 deletions
@@ -43,6 +43,12 @@ Version 3.2.1+edits (development branch) versus 3.2.1 that exceed the data port width (but still fit within a cache line) will occupy the cache for multiple cycles. This allows us to decouple the L2 cache bandwidth from the interconnect network port bandwidth. +- Updated configurations for Geforce GTX 480 and Tesla C2050 to have two + sub-partitions in every memory partition. The L2 cache bank in each + sub-partition has half the capacity of the original L2 cache bank. Each L2 + cache bank is configured to access at most 32B/cycle. With twice the number + of connections to the memory partitions, the interconnection network now runs + at half of its original speed. - Bug Fixes: - Fixed the flit count sent to GPUWattch for atomic operations. - Fix for Bug 51 - Updated the function declaration of diff --git a/configs/GTX480/config_fermi_islip.icnt b/configs/GTX480/config_fermi_islip.icnt index f2bb38e..07a4b10 100644 --- a/configs/GTX480/config_fermi_islip.icnt +++ b/configs/GTX480/config_fermi_islip.icnt @@ -5,7 +5,7 @@ network_count = 2; // Topology topology = fly; -k = 23; +k = 27; n = 1; // Routing diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index a1d6517..b0035a5 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -12,12 +12,13 @@ -gpgpu_n_clusters 15 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 # Fermi clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:1400.0:700.0:924.0 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -53,8 +54,8 @@ #-gpgpu_cache:dl1 64:128:6,L:L:m:N,A:32:8,8 #-gpgpu_shmem_size 16384 -# 64 sets, each 128 bytes 16-way for each memory partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W,A:32:4,4 +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4 @@ -99,7 +100,7 @@ -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBBCCCC.CCSSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 diff --git a/configs/TeslaC2050/config_fermi_islip.icnt b/configs/TeslaC2050/config_fermi_islip.icnt index f2bb38e..c1a272c 100644 --- a/configs/TeslaC2050/config_fermi_islip.icnt +++ b/configs/TeslaC2050/config_fermi_islip.icnt @@ -5,7 +5,7 @@ network_count = 2; // Topology topology = fly; -k = 23; +k = 26; n = 1; // Routing diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 70e3420..416b171 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -15,12 +15,13 @@ -gpgpu_n_clusters 14 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 # Fermi clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 575.0:1150.0:575.0:750.0 +-gpgpu_clock_domains 575.0:575.0:575.0:750.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -56,8 +57,8 @@ #-gpgpu_cache:dl1 64:128:6,L:L:m:N,A:32:8,8 #-gpgpu_shmem_size 16384 -# 64 sets, each 128 bytes 16-way for each memory partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W,A:32:4,4 +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4 @@ -102,7 +103,7 @@ -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBBCCCC.CCSSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 |