diff options
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 5 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 9fb928a..1ac4fdb 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -350,6 +350,8 @@ public: unsigned is_trace_driven_mode() const { return trace_driven_mode; } char* get_traces_filename() const { return g_traces_filename; } + bool flush_l1() const { return gpgpu_flush_l1_cache; } + private: void init_clock_domains(void ); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 19f8e72..0ea819d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3470,8 +3470,9 @@ bool shader_core_ctx::warp_waiting_at_mem_barrier( unsigned warp_id ) return false; if( !m_scoreboard->pendingWrites(warp_id) ) { m_warp[warp_id].clear_membar(); - if (m_gpu->get_config().gpgpu_flush_l1_cache) { - //invalidate L1 cache + if (m_gpu->get_config().flush_l1()) { + //Mahmoud fixed this on Nov 2019 + //Invalidate L1 cache //Based on Nvidia Doc, at MEM barrier, we have to //(1) wait for all pending writes till they are acked //(2) invalidate L1 cache to ensure coherence and avoid reading stall data |