diff options
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 4 | ||||
| -rw-r--r-- | configs/QuadroFX5800/gpgpusim.config | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 7 |
4 files changed, 12 insertions, 7 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index e1bcf1c..d658c7f 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -67,8 +67,8 @@ # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 -# {nbk:nbkgrp:tCCD:tCCDL:tRRD:tRCD:tRAS:tRP:tRTPL:tRC:CL:WL:tCDLR:tWR} --gpgpu_dram_timing_opt 16:4:2:3:5:12:28:12:2:35:10:7:6:12 +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12:4:3:2 # GDDR3 #-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 6c33a85..e14d2f1 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -37,8 +37,8 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS # GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -# {nbk:nbkgrp:tCCD:tCCDL:tRRD:tRCD:tRAS:tRP:tRTPL:tRC:CL:WL:tCDLR:tWR} --gpgpu_dram_timing_opt 8:1:2:0:8:12:25:10:0:35:10:7:6:11 +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11:1:0:0 # stat collection -gpgpu_memlatency_stat 14 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e71818b..c33ef17 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -123,8 +123,8 @@ void memory_config::reg_options(class OptionParser * opp) "Burst length of each DRAM request (default = 4 DDR cycle)", "4"); option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, - "DRAM timing parameters = {nbk:nbkgrp:tCCD:tCCDL:tRRD:tRCD:tRAS:tRP:tRTPL:tRC:CL:WL:tCDLR:tWR}", - "4:1:2:0:8:12:21:13:0:34:9:4:5:13"); + "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", + "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency, "ROP queue latency (default 85)", "85"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index fe66d04..208cfb8 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -71,15 +71,20 @@ struct memory_config { } void init() { + //Disabling bank groups if their values are not specified + nbkgrp = 1; + tCCDL = 0; + tRTPL = 0; assert(gpgpu_dram_timing_opt); sscanf(gpgpu_dram_timing_opt,"%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d", - &nbk,&nbkgrp,&tCCD,&tCCDL,&tRRD,&tRCD,&tRAS,&tRP,&tRTPL,&tRC,&CL,&WL,&tCDLR,&tWR); + &nbk,&tCCD,&tRRD,&tRCD,&tRAS,&tRP,&tRC,&CL,&WL,&tCDLR,&tWR,&nbkgrp,&tCCDL,&tRTPL); int nbkt = nbk/nbkgrp; unsigned i; for (i=0; nbkt>0; i++) { nbkt = nbkt>>1; } bk_tag_length = i; + assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/2)+2-WL); tWTR = (WL+(BL/2)+tCDLR); |