diff options
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 11 | ||||
| -rw-r--r-- | configs/Fermi/icnt_config_fermi_islip.txt (renamed from configs/Fermi/icnt_config_quadro_islip.txt) | 0 |
2 files changed, 5 insertions, 6 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index 78df079..d2ee23f 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -4,8 +4,8 @@ -gpgpu_ptx_force_max_capability 15 # high level architecture configuration --gpgpu_n_clusters 15 --gpgpu_n_cores_per_cluster 1 +-gpgpu_n_clusters 4 +-gpgpu_n_cores_per_cluster 4 -gpgpu_n_mem 6 # Fermi clock domains @@ -14,12 +14,12 @@ # shader core pipeline config -gpgpu_shader_registers 32768 --gpgpu_shader_core_pipeline 1024:32:32 --gpgpu_shader_cta 16 +-gpgpu_shader_core_pipeline 1536:32:32 +-gpgpu_shader_cta 8 -gpgpu_simd_model 1 -# In Fermi, the cache and shared memory could be configured to 16kb:48kb or 48kb:16kb +# In Fermi, the cache and shared memory could be configured to 16kb:48kb(default) or 48kb:16kb # <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq> -gpgpu_cache:dl1 32:128:4:L:R:f,A:32:8,8 -gpgpu_shmem_size 49152 @@ -57,7 +57,6 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# ANDREW # GDDR5 timing from hynix H5GQ1H24AFR # {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR} -gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12 diff --git a/configs/Fermi/icnt_config_quadro_islip.txt b/configs/Fermi/icnt_config_fermi_islip.txt index f2bb38e..f2bb38e 100644 --- a/configs/Fermi/icnt_config_quadro_islip.txt +++ b/configs/Fermi/icnt_config_fermi_islip.txt |