diff options
| -rw-r--r-- | CHANGES | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_fetch.h | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 33 |
3 files changed, 20 insertions, 15 deletions
@@ -8,6 +8,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack + - Fixed a bug where for each icache miss we also count a hit Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index f788c2b..c89edbb 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -82,6 +82,7 @@ public: bool is_write() {return m_access.is_write();} void set_addr(new_addr_type addr) { m_access.set_addr(addr); } new_addr_type get_addr() const { return m_access.get_addr(); } + unsigned get_access_size() const { return m_access.get_size(); } new_addr_type get_partition_addr() const { return m_partition_addr; } unsigned get_sub_partition_id() const { return m_raw_addr.sub_partition; } bool get_is_write() const { return m_access.is_write(); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b761dac..1c4465b 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -633,12 +633,12 @@ void shader_core_ctx::fetch() // mem_fetch *mf = m_mem_fetch_allocator->alloc() mem_access_t acc(INST_ACC_R,ppc,nbytes,false); mem_fetch *mf = new mem_fetch(acc, - NULL/*we don't have an instruction yet*/, - READ_PACKET_SIZE, - warp_id, - m_sid, - m_tpc, - m_memory_config ); + NULL/*we don't have an instruction yet*/, + READ_PACKET_SIZE, + warp_id, + m_sid, + m_tpc, + m_memory_config ); std::list<cache_event> events; enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle,events); if( status == MISS ) { @@ -665,6 +665,9 @@ void shader_core_ctx::fetch() if( m_L1I->access_ready() ) { mem_fetch *mf = m_L1I->next_access(); m_warp[mf->get_wid()].clear_imiss_pending(); + m_inst_fetch_buffer = ifetch_buffer_t(m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); + m_inst_fetch_buffer.m_valid = true; + m_warp[mf->get_wid()].set_last_fetch(gpu_sim_cycle); delete mf; } } @@ -680,7 +683,7 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* { warp_inst_t** pipe_reg = pipe_reg_set.get_free(); assert(pipe_reg); - + m_warp[warp_id].ibuffer_free(); assert(next_inst->valid()); **pipe_reg = *next_inst; // static instruction information @@ -688,7 +691,7 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* m_stats->shader_cycle_distro[2+(*pipe_reg)->active_count()]++; func_exec_inst( **pipe_reg ); if( next_inst->op == BARRIER_OP ){ - m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); + m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(),warp_id,const_cast<warp_inst_t*> (next_inst)); }else if( next_inst->op == MEMORY_BARRIER_OP ){ @@ -731,21 +734,21 @@ shd_warp_t& scheduler_unit::warp(int i){ * limit this number. If the number if < m_supervised_warps.size(), then only * the warps with highest RR priority will be placed in the result_list. */ -template < class T > + template < class T > void scheduler_unit::order_lrr( std::vector< T >& result_list, - const typename std::vector< T >& input_list, - const typename std::vector< T >::const_iterator& last_issued_from_input, - unsigned num_warps_to_add ) + const typename std::vector< T >& input_list, + const typename std::vector< T >::const_iterator& last_issued_from_input, + unsigned num_warps_to_add ) { assert( num_warps_to_add <= input_list.size() ); result_list.clear(); typename std::vector< T >::const_iterator iter = ( last_issued_from_input == input_list.end() ) ? input_list.begin() - : last_issued_from_input + 1; + : last_issued_from_input + 1; for ( unsigned count = 0; - count < num_warps_to_add; - ++iter, ++count) { + count < num_warps_to_add; + ++iter, ++count) { if ( iter == input_list.end() ) { iter = input_list.begin(); } |