summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config4
-rw-r--r--configs/tested-cfgs/SM6_TITANX/trace.config4
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/trace.config25
-rw-r--r--configs/tested-cfgs/SM7_QV100/trace.config19
-rw-r--r--configs/tested-cfgs/SM7_TITANV/trace.config19
-rw-r--r--src/trace-driven/ISA_Def/kepler_opcode.h148
-rw-r--r--src/trace-driven/ISA_Def/pascal_opcode.h199
-rw-r--r--src/trace-driven/ISA_Def/trace_opcode.h230
-rw-r--r--src/trace-driven/ISA_Def/turing_opcode.h221
-rw-r--r--src/trace-driven/ISA_Def/volta_opcode.h177
-rw-r--r--src/trace-driven/main.cc163
-rw-r--r--src/trace-driven/trace_driven.cc811
-rw-r--r--src/trace-driven/trace_driven.h210
13 files changed, 0 insertions, 2230 deletions
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config
deleted file mode 100644
index 4c80036..0000000
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/trace.config
+++ /dev/null
@@ -1,4 +0,0 @@
--trace_opcode_latency_initiation_int 4,1
--trace_opcode_latency_initiation_sp 4,1
--trace_opcode_latency_initiation_dp 20,2
--trace_opcode_latency_initiation_sfu 200,2
diff --git a/configs/tested-cfgs/SM6_TITANX/trace.config b/configs/tested-cfgs/SM6_TITANX/trace.config
deleted file mode 100644
index 88bcdc0..0000000
--- a/configs/tested-cfgs/SM6_TITANX/trace.config
+++ /dev/null
@@ -1,4 +0,0 @@
--trace_opcode_latency_initiation_int 4,1
--trace_opcode_latency_initiation_sp 4,1
--trace_opcode_latency_initiation_dp 20,8
--trace_opcode_latency_initiation_sfu 20,4
diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config
deleted file mode 100644
index 17b6cc7..0000000
--- a/configs/tested-cfgs/SM75_RTX2060/trace.config
+++ /dev/null
@@ -1,25 +0,0 @@
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
-#execute branch insts on spec unit 1
-#in Turing, there is a dedicated branch unit
-#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME>
--specialized_unit_1 1,4,4,4,4,BRA
-#<latency>,<initiation>
--trace_opcode_latency_initiation_spec_op_1 4,4
-
-#TEX unit, make fixed latency for all tex insts
--specialized_unit_2 1,1,200,4,4,TEX
--trace_opcode_latency_initiation_spec_op_2 200,4
-
-#tensor unit
--specialized_unit_3 1,4,8,4,4,TENSOR
--trace_opcode_latency_initiation_spec_op_3 8,4
-
-#UDP unit
-#for more info about UDP, see https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf
--specialized_unit_4 1,4,4,4,4,UDP
--trace_opcode_latency_initiation_spec_op_4 4,2
diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config
deleted file mode 100644
index 88f5706..0000000
--- a/configs/tested-cfgs/SM7_QV100/trace.config
+++ /dev/null
@@ -1,19 +0,0 @@
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
-#execute branch insts on spec unit 1
-#in Volta, there is a dedicated branch unit
-#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME>
--specialized_unit_1 1,4,4,4,4,BRA
--trace_opcode_latency_initiation_spec_op_1 4,4
-
-#TEX unit, make fixed latency for all tex insts
--specialized_unit_2 1,4,200,4,4,TEX
--trace_opcode_latency_initiation_spec_op_2 200,4
-
-#tensor unit
--specialized_unit_3 1,4,8,4,4,TENSOR
--trace_opcode_latency_initiation_spec_op_3 8,4
diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config
deleted file mode 100644
index 88f5706..0000000
--- a/configs/tested-cfgs/SM7_TITANV/trace.config
+++ /dev/null
@@ -1,19 +0,0 @@
--trace_opcode_latency_initiation_int 4,2
--trace_opcode_latency_initiation_sp 4,2
--trace_opcode_latency_initiation_dp 8,4
--trace_opcode_latency_initiation_sfu 20,8
--trace_opcode_latency_initiation_tensor 8,4
-
-#execute branch insts on spec unit 1
-#in Volta, there is a dedicated branch unit
-#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME>
--specialized_unit_1 1,4,4,4,4,BRA
--trace_opcode_latency_initiation_spec_op_1 4,4
-
-#TEX unit, make fixed latency for all tex insts
--specialized_unit_2 1,4,200,4,4,TEX
--trace_opcode_latency_initiation_spec_op_2 200,4
-
-#tensor unit
--specialized_unit_3 1,4,8,4,4,TENSOR
--trace_opcode_latency_initiation_spec_op_3 8,4
diff --git a/src/trace-driven/ISA_Def/kepler_opcode.h b/src/trace-driven/ISA_Def/kepler_opcode.h
deleted file mode 100644
index c2f8548..0000000
--- a/src/trace-driven/ISA_Def/kepler_opcode.h
+++ /dev/null
@@ -1,148 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#ifndef KEPLER_OPCODE_H
-#define KEPLER_OPCODE_H
-
-#include <string>
-#include <unordered_map>
-#include "trace_opcode.h"
-
-#define KEPLER_BINART_VERSION 35
-#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
-
-// TO DO: moving this to a yml or def files
-
-/// Kepler ISA
-// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
-static const std::unordered_map<std::string, OpcodeChar> Kepler_OpcodeMap = {
- // Floating Point 32 Instructions
- {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
- {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
- {"FADD", OpcodeChar(OP_FADD, SP_OP)},
- {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
- {"FCMP", OpcodeChar(OP_FCMP, SP_OP)},
- {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
- {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
- {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
- {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)},
- {"FSET", OpcodeChar(OP_FSET, SP_OP)},
- {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
- {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
- {"RRO", OpcodeChar(OP_RRO, SP_OP)},
- // SFU
- {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
-
- // Double Point Instructions
- {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
- {"DADD", OpcodeChar(OP_DADD, DP_OP)},
- {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
- {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)},
- {"DSET", OpcodeChar(OP_DSET, DP_OP)},
- {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
-
- // Integer Instructions
- {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
- {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
- {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
- {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
- {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
- {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
- {"ISUB", OpcodeChar(OP_ISUB, INTP_OP)},
- {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
- {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
- {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)},
- {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
- {"BFE", OpcodeChar(OP_BFE, INTP_OP)},
- {"BFI", OpcodeChar(OP_BFI, INTP_OP)},
- {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
- {"SHL", OpcodeChar(OP_SHL, INTP_OP)},
- {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
- {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
- {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
- {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
- {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
- {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
- {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)},
- {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
-
- // Conversion Instructions
- {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
- {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
- {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
- {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
-
- // Movement Instructions
- {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
- {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
- {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
- {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
- {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
-
- // Predicate Instructions
- {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
- {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
- {"CSET", OpcodeChar(OP_CSET, ALU_OP)},
- {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
- {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
-
- // Texture Instructions
- // For now, we ignore texture loads, consider it as ALU_OP
- {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
- {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
- {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
- {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
-
- // Load/Store Instructions
- // For now, we ignore constant loads, consider it as ALU_OP, TO DO
- {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
- // in Kepler, LD is load global so set it to LDG
- {"LD", OpcodeChar(OP_LDG, LOAD_OP)},
- {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
- {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
- {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
- {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)},
- {"ST", OpcodeChar(OP_STG, STORE_OP)},
- {"STL", OpcodeChar(OP_STL, STORE_OP)},
- {"STS", OpcodeChar(OP_STS, STORE_OP)},
- {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)},
- {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
- {"RED", OpcodeChar(OP_RED, STORE_OP)},
- {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
- {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
- {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
-
- // surface memory instructions
- {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)},
- {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)},
- {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)},
- {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)},
- {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)},
-
- // Control Instructions
- {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
- {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
- {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
- {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
- {"CAL", OpcodeChar(OP_CAL, CALL_OPS)},
- {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)},
- {"RET", OpcodeChar(OP_RET, RET_OPS)},
- {"BRK", OpcodeChar(OP_BRK, RET_OPS)},
- {"CONT", OpcodeChar(OP_CONT, RET_OPS)},
- {"SSY", OpcodeChar(OP_SSY, RET_OPS)},
- {"PBK", OpcodeChar(OP_PBK, RET_OPS)},
- {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)},
- {"PRET", OpcodeChar(OP_PRET, RET_OPS)},
- {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
- {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
-
- // Miscellaneous Instructions
- {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
- {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
- {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
- {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
- {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
-};
-
-#endif
diff --git a/src/trace-driven/ISA_Def/pascal_opcode.h b/src/trace-driven/ISA_Def/pascal_opcode.h
deleted file mode 100644
index 34fe400..0000000
--- a/src/trace-driven/ISA_Def/pascal_opcode.h
+++ /dev/null
@@ -1,199 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#ifndef PASCAL_OPCODE_H
-#define PASCAL_OPCODE_H
-
-#include <string>
-#include <unordered_map>
-#include "trace_opcode.h"
-
-#define PASCAL_TITANX_BINART_VERSION 61
-#define PASCAL_P100_BINART_VERSION 60
-
-#define PASCAL_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
-
-// TO DO: moving this to a yml or def files
-
-/// Pascal SM_61 ISA
-// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
-static const std::unordered_map<std::string, OpcodeChar> Pascal_OpcodeMap = {
- // Floating Point 32 Instructions
- {"FADD", OpcodeChar(OP_FADD, SP_OP)},
- {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
- {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
- {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
- {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
- {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
- {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
- {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
- {"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
- {"FSET", OpcodeChar(OP_FSET, SP_OP)},
- {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
- {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
- {"RRO", OpcodeChar(OP_RRO, SP_OP)},
-
- // SFU
- {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
-
- // Floating Point 16 Instructions
- {"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
- {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
- {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
- {"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
- {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
-
- // Double Point Instructions
- {"DADD", OpcodeChar(OP_DADD, DP_OP)},
- {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
- {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
- {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
- {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)},
- {"DSET", OpcodeChar(OP_DSET, DP_OP)},
-
- // Integer Instructions
- {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
- {"BREV", OpcodeChar(OP_BREV, INTP_OP)},
- {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
- {"IABS", OpcodeChar(OP_IABS, INTP_OP)},
- {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
- {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
- {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
- {"IDP", OpcodeChar(OP_IDP, INTP_OP)},
- {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
- {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
- {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
- {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
- {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
- {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
- {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
- {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
- {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
- {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
- {"LEA", OpcodeChar(OP_LEA, INTP_OP)},
- {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
- {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
- {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
- {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
- {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
- {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
- {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
- {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
- {"BFE", OpcodeChar(OP_BFE, INTP_OP)},
- {"BFI", OpcodeChar(OP_BFI, INTP_OP)},
- {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)},
- {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
- {"SHL", OpcodeChar(OP_SHL, INTP_OP)},
- {"XMAD", OpcodeChar(OP_XMAD, INTP_OP)},
- {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)},
-
- // Conversion Instructions
- {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
- {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
- {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
- {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
- {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
- {"FRND", OpcodeChar(OP_FRND, ALU_OP)},
-
- // Movement Instructions
- {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
- {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
- {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
- {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
- {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
- {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
-
- // Predicate Instructions
- {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
- {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
- {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
- {"CSET", OpcodeChar(OP_CSET, ALU_OP)},
- {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
- {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
-
- // Load/Store Instructions
- {"LD", OpcodeChar(OP_LD, LOAD_OP)},
- // For now, we ignore constant loads, consider it as ALU_OP, TO DO
- {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
- {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
- {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
- {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
- {"ST", OpcodeChar(OP_ST, STORE_OP)},
- {"STG", OpcodeChar(OP_STG, STORE_OP)},
- {"STL", OpcodeChar(OP_STL, STORE_OP)},
- {"STS", OpcodeChar(OP_STS, STORE_OP)},
- {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
- {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
- {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
- {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
- {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
- {"RED", OpcodeChar(OP_RED, STORE_OP)},
- {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
- {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
- {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
- {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
- {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
-
- // Texture Instructions
- // For now, we ignore texture loads, consider it as ALU_OP
- {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
- {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
- {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
- {"TMML", OpcodeChar(OP_TMML, ALU_OP)},
- {"TXD", OpcodeChar(OP_TXD, ALU_OP)},
- {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
- {"TEXS", OpcodeChar(OP_TEXS, ALU_OP)},
- {"TLD4S", OpcodeChar(OP_TLD4S, ALU_OP)},
- {"TLDS", OpcodeChar(OP_TLDS, ALU_OP)},
-
- // Control Instructions
- {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)},
- {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
- {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
- {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)},
- {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
- {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)},
- {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)},
- {"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
- {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
- {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
- {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)},
- {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)},
- {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
- {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
- {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
- {"RET", OpcodeChar(OP_RET, RET_OPS)},
- {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)},
- {"RTT", OpcodeChar(OP_RTT, RET_OPS)},
- {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)},
- {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)},
- {"CAL", OpcodeChar(OP_CAL, CALL_OPS)},
- {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)},
- {"PRET", OpcodeChar(OP_PRET, CALL_OPS)},
- {"BRK", OpcodeChar(OP_BRK, CALL_OPS)},
- {"PBK", OpcodeChar(OP_PBK, CALL_OPS)},
- {"CONT", OpcodeChar(OP_CONT, CALL_OPS)},
- {"PCNT", OpcodeChar(OP_PCNT, CALL_OPS)},
- {"PEXIT", OpcodeChar(OP_PEXIT, CALL_OPS)},
-
- // Miscellaneous Instructions
- {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
- {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
- {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
- {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
- {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
- {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
- {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)},
- {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
- {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
- {"R2B", OpcodeChar(OP_R2B, ALU_OP)},
- {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
- {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
- {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
- {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
- {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
-
-};
-
-#endif
diff --git a/src/trace-driven/ISA_Def/trace_opcode.h b/src/trace-driven/ISA_Def/trace_opcode.h
deleted file mode 100644
index 5675957..0000000
--- a/src/trace-driven/ISA_Def/trace_opcode.h
+++ /dev/null
@@ -1,230 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#ifndef TRACE_OPCODE_H
-#define TRACE_OPCODE_H
-
-#include <string>
-#include <unordered_map>
-#include "../../abstract_hardware_model.h"
-
-enum TraceInstrOpcode {
- // Volta (includes common insts for others cards as well)
- OP_FADD = 1,
- OP_FADD32I,
- OP_FCHK,
- OP_FFMA32I,
- OP_FFMA,
- OP_FMNMX,
- OP_FMUL,
- OP_FMUL32I,
- OP_FSEL,
- OP_FSET,
- OP_FSETP,
- OP_FSWZADD,
- OP_MUFU,
- OP_HADD2,
- OP_HADD2_32I,
- OP_HFMA2,
- OP_HFMA2_32I,
- OP_HMUL2,
- OP_HMUL2_32I,
- OP_HSET2,
- OP_HSETP2,
- OP_HMMA,
- OP_DADD,
- OP_DFMA,
- OP_DMUL,
- OP_DSETP,
- OP_BMSK,
- OP_BREV,
- OP_FLO,
- OP_IABS,
- OP_IADD,
- OP_IADD3,
- OP_IADD32I,
- OP_IDP,
- OP_IDP4A,
- OP_IMAD,
- OP_IMMA,
- OP_IMNMX,
- OP_IMUL,
- OP_IMUL32I,
- OP_ISCADD,
- OP_ISCADD32I,
- OP_ISETP,
- OP_LEA,
- OP_LOP,
- OP_LOP3,
- OP_LOP32I,
- OP_POPC,
- OP_SHF,
- OP_SHR,
- OP_VABSDIFF,
- OP_VABSDIFF4,
- OP_F2F,
- OP_F2I,
- OP_I2F,
- OP_I2I,
- OP_I2IP,
- OP_FRND,
- OP_MOV,
- OP_MOV32I,
- OP_PRMT,
- OP_SEL,
- OP_SGXT,
- OP_SHFL,
- OP_PLOP3,
- OP_PSETP,
- OP_P2R,
- OP_R2P,
- OP_LD,
- OP_LDC,
- OP_LDG,
- OP_LDL,
- OP_LDS,
- OP_ST,
- OP_STG,
- OP_STL,
- OP_STS,
- OP_MATCH,
- OP_QSPC,
- OP_ATOM,
- OP_ATOMS,
- OP_ATOMG,
- OP_RED,
- OP_CCTL,
- OP_CCTLL,
- OP_ERRBAR,
- OP_MEMBAR,
- OP_CCTLT,
- OP_TEX,
- OP_TLD,
- OP_TLD4,
- OP_TMML,
- OP_TXD,
- OP_TXQ,
- OP_BMOV,
- OP_BPT,
- OP_BRA,
- OP_BREAK,
- OP_BRX,
- OP_BSSY,
- OP_BSYNC,
- OP_CALL,
- OP_EXIT,
- OP_JMP,
- OP_JMX,
- OP_KILL,
- OP_NANOSLEEP,
- OP_RET,
- OP_RPCMOV,
- OP_RTT,
- OP_WARPSYNC,
- OP_YIELD,
- OP_B2R,
- OP_BAR,
- OP_CS2R,
- OP_CSMTEST,
- OP_DEPBAR,
- OP_GETLMEMBASE,
- OP_LEPC,
- OP_NOP,
- OP_PMTRIG,
- OP_R2B,
- OP_S2R,
- OP_SETCTAID,
- OP_SETLMEMBASE,
- OP_VOTE,
- OP_VOTE_VTG,
- // unique insts for pascal
- OP_RRO,
- OP_DMNMX,
- OP_DSET,
- OP_BFE,
- OP_BFI,
- OP_ICMP,
- OP_IMADSP,
- OP_SHL,
- OP_XMAD,
- OP_CSET,
- OP_CSETP,
- OP_TEXS,
- OP_TLD4S,
- OP_TLDS,
- OP_CAL,
- OP_JCAL,
- OP_PRET,
- OP_BRK,
- OP_PBK,
- OP_CONT,
- OP_PCNT,
- OP_PEXIT,
- OP_SSY,
- OP_SYNC,
- OP_PSET,
- OP_VMNMX,
- OP_ISET,
- // unique insts for turing
- OP_BMMA,
- OP_MOVM,
- OP_LDSM,
- OP_R2UR,
- OP_S2UR,
- OP_UBMSK,
- OP_UBREV,
- OP_UCLEA,
- OP_UFLO,
- OP_UIADD3,
- OP_UIMAD,
- OP_UISETP,
- OP_ULDC,
- OP_ULEA,
- OP_ULOP,
- OP_ULOP3,
- OP_ULOP32I,
- OP_UMOV,
- OP_UP2UR,
- OP_UPLOP3,
- OP_UPOPC,
- OP_UPRMT,
- OP_UPSETP,
- OP_UR2UP,
- OP_USEL,
- OP_USGXT,
- OP_USHF,
- OP_USHL,
- OP_USHR,
- OP_VOTEU,
- OP_SUATOM,
- OP_SULD,
- OP_SURED,
- OP_SUST,
- OP_BRXU,
- OP_JMXU,
- // unique insts for kepler
- OP_FCMP,
- OP_FSWZ,
- OP_ISAD,
- OP_LDSLK,
- OP_STSCUL,
- OP_SUCLAMP,
- OP_SUBFM,
- OP_SUEAU,
- OP_SULDGA,
- OP_SUSTGA,
- OP_ISUB,
- SASS_NUM_OPCODES /* The total number of opcodes. */
-};
-typedef enum TraceInstrOpcode sass_op_type;
-
-struct OpcodeChar {
- OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) {
- opcode = m_opcode;
- opcode_category = m_opcode_category;
- }
- unsigned opcode;
- unsigned opcode_category;
-};
-
-#endif
diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h
deleted file mode 100644
index 12bbe76..0000000
--- a/src/trace-driven/ISA_Def/turing_opcode.h
+++ /dev/null
@@ -1,221 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#ifndef TURING_OPCODE_H
-#define TURING_OPCODE_H
-
-#include <string>
-#include <unordered_map>
-#include "trace_opcode.h"
-
-#define TURING_BINART_VERSION 75
-#define TURING_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
-
-// TO DO: moving this to a yml or def files
-
-/// Volta SM_70 ISA
-// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
-static const std::unordered_map<std::string, OpcodeChar> Turing_OpcodeMap = {
- // Floating Point 32 Instructions
- {"FADD", OpcodeChar(OP_FADD, SP_OP)},
- {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
- {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
- {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
- {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
- {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
- {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
- {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
- {"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
- {"FSET", OpcodeChar(OP_FSET, SP_OP)},
- {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
- {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
- // SFU
- {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
-
- // Floating Point 16 Instructions
- {"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
- {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
- {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
- {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
- {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
- {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
- {"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
- {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
-
- // Tensor Core Instructions
- // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3
- {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)},
-
- // Double Point Instructions
- {"DADD", OpcodeChar(OP_DADD, DP_OP)},
- {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
- {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
- {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
-
- // Integer Instructions
- {"BMMA", OpcodeChar(OP_BMMA, INTP_OP)}, ////////
- {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
- {"BREV", OpcodeChar(OP_BREV, INTP_OP)},
- {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
- {"IABS", OpcodeChar(OP_IABS, INTP_OP)},
- {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
- {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
- {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
- {"IDP", OpcodeChar(OP_IDP, INTP_OP)},
- {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
- {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
- {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
- {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
- {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
- {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
- {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
- {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
- {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
- {"LEA", OpcodeChar(OP_LEA, INTP_OP)},
- {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
- {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
- {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
- {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
- {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
- {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, //////////
- {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
- {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
- {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
-
- // Conversion Instructions
- {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
- {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
- {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
- {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
- {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
- {"FRND", OpcodeChar(OP_FRND, ALU_OP)},
-
- // Movement Instructions
- {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
- {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
- {"MOVM", OpcodeChar(OP_MOVM, ALU_OP)}, // move matrix
- {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
- {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
- {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
- {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
-
- // Predicate Instructions
- {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
- {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
- {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
-
- // Load/Store Instructions
- {"LD", OpcodeChar(OP_LD, LOAD_OP)},
- // For now, we ignore constant loads, consider it as ALU_OP, TO DO
- {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
- {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
- {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
- {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
- {"LDSM", OpcodeChar(OP_LDSM, LOAD_OP)}, //
- {"ST", OpcodeChar(OP_ST, STORE_OP)},
- {"STG", OpcodeChar(OP_STG, STORE_OP)},
- {"STL", OpcodeChar(OP_STL, STORE_OP)},
- {"STS", OpcodeChar(OP_STS, STORE_OP)},
- {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
- {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
- {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
- {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
- {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
- {"RED", OpcodeChar(OP_RED, STORE_OP)},
- {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
- {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
- {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
- {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
- {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
-
- // Uniform Datapath Instruction
- // UDP unit
- // for more info about UDP, see
- // https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf
- {"R2UR", OpcodeChar(OP_R2UR, SPECIALIZED_UNIT_4_OP)},
- {"S2UR", OpcodeChar(OP_S2UR, SPECIALIZED_UNIT_4_OP)},
- {"UBMSK", OpcodeChar(OP_UBMSK, SPECIALIZED_UNIT_4_OP)},
- {"UBREV", OpcodeChar(OP_UBREV, SPECIALIZED_UNIT_4_OP)},
- {"UCLEA", OpcodeChar(OP_UCLEA, SPECIALIZED_UNIT_4_OP)},
- {"UFLO", OpcodeChar(OP_UFLO, SPECIALIZED_UNIT_4_OP)},
- {"UIADD3", OpcodeChar(OP_UIADD3, SPECIALIZED_UNIT_4_OP)},
- {"UIMAD", OpcodeChar(OP_UIMAD, SPECIALIZED_UNIT_4_OP)},
- {"UISETP", OpcodeChar(OP_UISETP, SPECIALIZED_UNIT_4_OP)},
- {"ULDC", OpcodeChar(OP_ULDC, SPECIALIZED_UNIT_4_OP)},
- {"ULEA", OpcodeChar(OP_ULEA, SPECIALIZED_UNIT_4_OP)},
- {"ULOP", OpcodeChar(OP_ULOP, SPECIALIZED_UNIT_4_OP)},
- {"ULOP3", OpcodeChar(OP_ULOP3, SPECIALIZED_UNIT_4_OP)},
- {"ULOP32I", OpcodeChar(OP_ULOP32I, SPECIALIZED_UNIT_4_OP)},
- {"UMOV", OpcodeChar(OP_UMOV, SPECIALIZED_UNIT_4_OP)},
- {"UP2UR", OpcodeChar(OP_UP2UR, SPECIALIZED_UNIT_4_OP)},
- {"UPLOP3", OpcodeChar(OP_UPLOP3, SPECIALIZED_UNIT_4_OP)},
- {"UPOPC", OpcodeChar(OP_UPOPC, SPECIALIZED_UNIT_4_OP)},
- {"UPRMT", OpcodeChar(OP_UPRMT, SPECIALIZED_UNIT_4_OP)},
- {"UPSETP", OpcodeChar(OP_UPSETP, SPECIALIZED_UNIT_4_OP)},
- {"UR2UP", OpcodeChar(OP_UR2UP, SPECIALIZED_UNIT_4_OP)},
- {"USEL", OpcodeChar(OP_USEL, SPECIALIZED_UNIT_4_OP)},
- {"USGXT", OpcodeChar(OP_USGXT, SPECIALIZED_UNIT_4_OP)},
- {"USHF", OpcodeChar(OP_USHF, SPECIALIZED_UNIT_4_OP)},
- {"USHL", OpcodeChar(OP_USHL, SPECIALIZED_UNIT_4_OP)},
- {"USHR", OpcodeChar(OP_USHR, SPECIALIZED_UNIT_4_OP)},
- {"VOTEU", OpcodeChar(OP_VOTEU, SPECIALIZED_UNIT_4_OP)},
-
- // Texture Instructions
- // For now, we ignore texture loads, consider it as ALU_OP
- {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)},
- {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)},
- {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)},
- {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)},
- {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)},
- {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)},
-
- // Surface Instructions //
- {"SUATOM", OpcodeChar(OP_SUATOM, ALU_OP)},
- {"SULD", OpcodeChar(OP_SULD, ALU_OP)},
- {"SURED", OpcodeChar(OP_SURED, ALU_OP)},
- {"SUST", OpcodeChar(OP_SUST, ALU_OP)},
-
- // Control Instructions
- // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1)
- {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)},
- {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)},
- {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)},
- {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)},
- {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)},
- {"BRXU", OpcodeChar(OP_BRXU, SPECIALIZED_UNIT_1_OP)}, //
- {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)},
- {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)},
- {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)},
- {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
- {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)},
- {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)},
- {"JMXU", OpcodeChar(OP_JMXU, SPECIALIZED_UNIT_1_OP)}, ///
- {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_3_OP)},
- {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)},
- {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)},
- {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)},
- {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)},
- {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)},
- {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)},
-
- // Miscellaneous Instructions
- {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
- {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
- {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
- {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
- {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
- {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
- {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)},
- {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
- {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
- {"R2B", OpcodeChar(OP_R2B, ALU_OP)},
- {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
- {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
- {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
- {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
- {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
-
-};
-
-#endif
diff --git a/src/trace-driven/ISA_Def/volta_opcode.h b/src/trace-driven/ISA_Def/volta_opcode.h
deleted file mode 100644
index 3358211..0000000
--- a/src/trace-driven/ISA_Def/volta_opcode.h
+++ /dev/null
@@ -1,177 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#ifndef VOLTA_OPCODE_H
-#define VOLTA_OPCODE_H
-
-#include <string>
-#include <unordered_map>
-#include "trace_opcode.h"
-
-#define VOLTA_BINART_VERSION 70
-#define VOLTA_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
-
-// TO DO: moving this to a yml or def files
-
-/// Volta SM_70 ISA
-// see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
-static const std::unordered_map<std::string, OpcodeChar> Volta_OpcodeMap = {
- // Floating Point 32 Instructions
- {"FADD", OpcodeChar(OP_FADD, SP_OP)},
- {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
- {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
- {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
- {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
- {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
- {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
- {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
- {"FSEL", OpcodeChar(OP_FSEL, SP_OP)},
- {"FSET", OpcodeChar(OP_FSET, SP_OP)},
- {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
- {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)},
- // SFU
- {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
-
- // Floating Point 16 Instructions
- {"HADD2", OpcodeChar(OP_HADD2, SP_OP)},
- {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)},
- {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)},
- {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)},
- {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)},
- {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)},
- {"HSET2", OpcodeChar(OP_HSET2, SP_OP)},
- {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)},
-
- // Tensor Core Instructions
- // Execute Tensor Core Instructions on SPECIALIZED_UNIT_3
- {"HMMA", OpcodeChar(OP_HMMA, SPECIALIZED_UNIT_3_OP)},
-
- // Double Point Instructions
- {"DADD", OpcodeChar(OP_DADD, DP_OP)},
- {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
- {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
- {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
-
- // Integer Instructions
- {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)},
- {"BREV", OpcodeChar(OP_BREV, INTP_OP)},
- {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
- {"IABS", OpcodeChar(OP_IABS, INTP_OP)},
- {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
- {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)},
- {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
- {"IDP", OpcodeChar(OP_IDP, INTP_OP)},
- {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)},
- {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
- {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)},
- {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
- {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
- {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
- {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
- {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
- {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
- {"LEA", OpcodeChar(OP_LEA, INTP_OP)},
- {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
- {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
- {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
- {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
- {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
- {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
- {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)},
- {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)},
-
- // Conversion Instructions
- {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
- {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
- {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
- {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
- {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)},
- {"FRND", OpcodeChar(OP_FRND, ALU_OP)},
-
- // Movement Instructions
- {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
- {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
- {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
- {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
- {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)},
- {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
-
- // Predicate Instructions
- {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
- {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
- {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
-
- // Load/Store Instructions
- {"LD", OpcodeChar(OP_LD, LOAD_OP)},
- // For now, we ignore constant loads, consider it as ALU_OP, TO DO
- {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
- {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
- {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
- {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
- {"ST", OpcodeChar(OP_ST, STORE_OP)},
- {"STG", OpcodeChar(OP_STG, STORE_OP)},
- {"STL", OpcodeChar(OP_STL, STORE_OP)},
- {"STS", OpcodeChar(OP_STS, STORE_OP)},
- {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)},
- {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)},
- {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
- {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)},
- {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)},
- {"RED", OpcodeChar(OP_RED, STORE_OP)},
- {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
- {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
- {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)},
- {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
- {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)},
-
- // Texture Instructions
- // For now, we ignore texture loads, consider it as ALU_OP
- {"TEX", OpcodeChar(OP_TEX, SPECIALIZED_UNIT_2_OP)},
- {"TLD", OpcodeChar(OP_TLD, SPECIALIZED_UNIT_2_OP)},
- {"TLD4", OpcodeChar(OP_TLD4, SPECIALIZED_UNIT_2_OP)},
- {"TMML", OpcodeChar(OP_TMML, SPECIALIZED_UNIT_2_OP)},
- {"TXD", OpcodeChar(OP_TXD, SPECIALIZED_UNIT_2_OP)},
- {"TXQ", OpcodeChar(OP_TXQ, SPECIALIZED_UNIT_2_OP)},
-
- // Control Instructions
- // execute branch insts on a dedicated branch unit (SPECIALIZED_UNIT_1)
- {"BMOV", OpcodeChar(OP_BMOV, SPECIALIZED_UNIT_1_OP)},
- {"BPT", OpcodeChar(OP_BPT, SPECIALIZED_UNIT_1_OP)},
- {"BRA", OpcodeChar(OP_BRA, SPECIALIZED_UNIT_1_OP)},
- {"BREAK", OpcodeChar(OP_BREAK, SPECIALIZED_UNIT_1_OP)},
- {"BRX", OpcodeChar(OP_BRX, SPECIALIZED_UNIT_1_OP)},
- {"BSSY", OpcodeChar(OP_BSSY, SPECIALIZED_UNIT_1_OP)},
- {"BSYNC", OpcodeChar(OP_BSYNC, SPECIALIZED_UNIT_1_OP)},
- {"CALL", OpcodeChar(OP_CALL, SPECIALIZED_UNIT_1_OP)},
- {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
- {"JMP", OpcodeChar(OP_JMP, SPECIALIZED_UNIT_1_OP)},
- {"JMX", OpcodeChar(OP_JMX, SPECIALIZED_UNIT_1_OP)},
- {"KILL", OpcodeChar(OP_KILL, SPECIALIZED_UNIT_1_OP)},
- {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, SPECIALIZED_UNIT_1_OP)},
- {"RET", OpcodeChar(OP_RET, SPECIALIZED_UNIT_1_OP)},
- {"RPCMOV", OpcodeChar(OP_RPCMOV, SPECIALIZED_UNIT_1_OP)},
- {"RTT", OpcodeChar(OP_RTT, SPECIALIZED_UNIT_1_OP)},
- {"WARPSYNC", OpcodeChar(OP_WARPSYNC, SPECIALIZED_UNIT_1_OP)},
- {"YIELD", OpcodeChar(OP_YIELD, SPECIALIZED_UNIT_1_OP)},
-
- // Miscellaneous Instructions
- {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
- {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
- {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)},
- {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)},
- {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)},
- {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)},
- {"LEPC", OpcodeChar(OP_LEPC, ALU_OP)},
- {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
- {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)},
- {"R2B", OpcodeChar(OP_R2B, ALU_OP)},
- {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
- {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)},
- {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)},
- {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
- {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)},
-
-};
-
-#endif
diff --git a/src/trace-driven/main.cc b/src/trace-driven/main.cc
deleted file mode 100644
index f12d39a..0000000
--- a/src/trace-driven/main.cc
+++ /dev/null
@@ -1,163 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#include <math.h>
-#include <stdio.h>
-#include <time.h>
-#include <fstream>
-#include <iostream>
-#include <sstream>
-#include <string>
-#include <vector>
-
-#include "../../libcuda/gpgpu_context.h"
-#include "../abstract_hardware_model.h"
-#include "../cuda-sim/cuda-sim.h"
-#include "../gpgpu-sim/gpu-sim.h"
-#include "../gpgpu-sim/icnt_wrapper.h"
-#include "../gpgpusim_entrypoint.h"
-#include "../option_parser.h"
-#include "ISA_Def/trace_opcode.h"
-#include "trace_driven.h"
-
-/* TO DO:
- * NOTE: the current version of trace-driven is functionally working fine,
- * but we still need to improve traces compression and simulation speed.
- * This includes:
- * 1- Prefetch concurrent thread that prefetches traces from disk (to not be
- * limited by disk speed) 2- traces compression format a. cfg format and remove
- * thread/block Id from the head b. using zlib library to save in binary format
- *
- * 3- Efficient memory improvement (save string not objects - parse only 10 in
- * the buffer) 4- Seeking capability - thread scheduler (save tb index and warp
- * index info in the traces header) 5- Get rid off traces intermediate files -
- * change the tracer
- */
-gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[],
- gpgpu_context* m_gpgpu_context,
- class trace_config* m_config);
-
-int main(int argc, const char** argv) {
- gpgpu_context* m_gpgpu_context = new gpgpu_context();
- trace_config tconfig;
-
- gpgpu_sim* m_gpgpu_sim =
- gpgpu_trace_sim_init_perf_model(argc, argv, m_gpgpu_context, &tconfig);
- m_gpgpu_sim->init();
-
- // for each kernel
- // load file
- // parse and create kernel info
- // launch
- // while loop till the end of the end kernel execution
- // prints stats
-
- trace_parser tracer(tconfig.get_traces_filename(), m_gpgpu_sim,
- m_gpgpu_context);
- tconfig.parse_config();
-
- std::vector<std::string> commandlist = tracer.parse_kernellist_file();
-
- for (unsigned i = 0; i < commandlist.size(); ++i) {
- trace_kernel_info_t* kernel_info = NULL;
- if (commandlist[i].substr(0, 6) == "Memcpy") {
- size_t addre, Bcount;
- tracer.parse_memcpy_info(commandlist[i], addre, Bcount);
- std::cout << commandlist[i] << std::endl;
- m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount);
- continue;
- } else {
- kernel_info = tracer.parse_kernel_info(commandlist[i], &tconfig);
- m_gpgpu_sim->launch(kernel_info);
- }
-
- bool active = false;
- bool sim_cycles = false;
- bool break_limit = false;
-
- do {
- if (!m_gpgpu_sim->active()) break;
-
- // performance simulation
- if (m_gpgpu_sim->active()) {
- m_gpgpu_sim->cycle();
- sim_cycles = true;
- m_gpgpu_sim->deadlock_check();
- } else {
- if (m_gpgpu_sim->cycle_insn_cta_max_hit()) {
- m_gpgpu_context->the_gpgpusim->g_stream_manager
- ->stop_all_running_kernels();
- break_limit = true;
- }
- }
-
- active = m_gpgpu_sim->active();
-
- } while (active);
-
- if (kernel_info) {
- tracer.kernel_finalizer(kernel_info);
- m_gpgpu_sim->print_stats();
- }
-
- if (sim_cycles) {
- m_gpgpu_sim->update_stats();
- m_gpgpu_context->print_simulation_time();
- }
-
- if (break_limit) {
- printf(
- "GPGPU-Sim: ** break due to reaching the maximum cycles (or "
- "instructions) **\n");
- fflush(stdout);
- exit(1);
- }
- }
-
- // we print this message to inform the gpgpu-simulation stats_collect script
- // that we are done
- printf("GPGPU-Sim: *** simulation thread exiting ***\n");
- printf("GPGPU-Sim: *** exit detected ***\n");
-
- return 1;
-}
-
-gpgpu_sim* gpgpu_trace_sim_init_perf_model(int argc, const char* argv[],
- gpgpu_context* m_gpgpu_context,
- trace_config* m_config) {
- srand(1);
- print_splash();
-
- option_parser_t opp = option_parser_create();
-
- m_gpgpu_context->ptx_reg_options(opp);
- m_gpgpu_context->func_sim->ptx_opcocde_latency_options(opp);
-
- icnt_reg_options(opp);
-
- m_gpgpu_context->the_gpgpusim->g_the_gpu_config =
- new gpgpu_sim_config(m_gpgpu_context);
- m_gpgpu_context->the_gpgpusim->g_the_gpu_config->reg_options(
- opp); // register GPU microrachitecture options
- m_config->reg_options(opp);
-
- option_parser_cmdline(opp, argc, argv); // parse configuration options
- fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n");
- option_parser_print(opp, stdout);
- // Set the Numeric locale to a standard locale where a decimal point is a
- // "dot" not a "comma" so it does the parsing correctly independent of the
- // system environment variables
- assert(setlocale(LC_NUMERIC, "C"));
- m_gpgpu_context->the_gpgpusim->g_the_gpu_config->init();
-
- m_gpgpu_context->the_gpgpusim->g_the_gpu = new trace_gpgpu_sim(
- *(m_gpgpu_context->the_gpgpusim->g_the_gpu_config), m_gpgpu_context);
-
- m_gpgpu_context->the_gpgpusim->g_stream_manager =
- new stream_manager((m_gpgpu_context->the_gpgpusim->g_the_gpu),
- m_gpgpu_context->func_sim->g_cuda_launch_blocking);
-
- m_gpgpu_context->the_gpgpusim->g_simulation_starttime = time((time_t*)NULL);
-
- return m_gpgpu_context->the_gpgpusim->g_the_gpu;
-}
diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
deleted file mode 100644
index 83b134e..0000000
--- a/src/trace-driven/trace_driven.cc
+++ /dev/null
@@ -1,811 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-// [email protected]
-
-#include <bits/stdc++.h>
-#include <math.h>
-#include <stdio.h>
-#include <time.h>
-#include <fstream>
-#include <iostream>
-#include <sstream>
-#include <string>
-#include <vector>
-
-#include "../../libcuda/gpgpu_context.h"
-#include "../abstract_hardware_model.h"
-#include "../cuda-sim/cuda-sim.h"
-#include "../cuda-sim/ptx_ir.h"
-#include "../cuda-sim/ptx_parser.h"
-#include "../gpgpu-sim/gpu-sim.h"
-#include "../gpgpusim_entrypoint.h"
-#include "../option_parser.h"
-#include "ISA_Def/kepler_opcode.h"
-#include "ISA_Def/pascal_opcode.h"
-#include "ISA_Def/trace_opcode.h"
-#include "ISA_Def/turing_opcode.h"
-#include "ISA_Def/volta_opcode.h"
-#include "trace_driven.h"
-
-bool is_number(const std::string& s) {
- std::string::const_iterator it = s.begin();
- while (it != s.end() && std::isdigit(*it)) ++it;
- return !s.empty() && it == s.end();
-}
-
-void split(const std::string& str, std::vector<std::string>& cont,
- char delimi = ' ') {
- std::stringstream ss(str);
- std::string token;
- while (std::getline(ss, token, delimi)) {
- cont.push_back(token);
- }
-}
-
-trace_parser::trace_parser(const char* kernellist_filepath,
- gpgpu_sim* m_gpgpu_sim,
- gpgpu_context* m_gpgpu_context) {
- this->m_gpgpu_sim = m_gpgpu_sim;
- this->m_gpgpu_context = m_gpgpu_context;
- kernellist_filename = kernellist_filepath;
-}
-
-std::vector<std::string> trace_parser::parse_kernellist_file() {
- ifs.open(kernellist_filename);
-
- if (!ifs.is_open()) {
- std::cout << "Unable to open file: " << kernellist_filename << std::endl;
- exit(1);
- }
-
- std::string directory(kernellist_filename);
- const size_t last_slash_idx = directory.rfind('/');
- if (std::string::npos != last_slash_idx) {
- directory = directory.substr(0, last_slash_idx);
- }
-
- std::string line, filepath;
- std::vector<std::string> kernellist;
- while (!ifs.eof()) {
- getline(ifs, line);
- if (line.empty())
- continue;
- else if (line.substr(0, 6) == "Memcpy") {
- kernellist.push_back(line);
- } else if (line.substr(0, 6) == "kernel") {
- filepath = directory + "/" + line;
- kernellist.push_back(filepath);
- }
- }
-
- ifs.close();
- return kernellist;
-}
-
-void trace_parser::parse_memcpy_info(const std::string& memcpy_command,
- size_t& address, size_t& count) {
- std::vector<std::string> params;
- split(memcpy_command, params, ',');
- assert(params.size() == 3);
- std::stringstream ss;
- ss.str(params[1]);
- ss >> std::hex >> address;
- ss.clear();
- ss.str(params[2]);
- ss >> std::dec >> count;
-}
-
-trace_kernel_info_t* trace_parser::parse_kernel_info(
- const std::string& kerneltraces_filepath, trace_config* config) {
- ifs.open(kerneltraces_filepath.c_str());
-
- if (!ifs.is_open()) {
- std::cout << "Unable to open file: " << kerneltraces_filepath << std::endl;
- exit(1);
- }
-
- std::cout << "Processing kernel " << kerneltraces_filepath << std::endl;
-
- unsigned grid_dim_x = 0, grid_dim_y = 0, grid_dim_z = 0, tb_dim_x = 0,
- tb_dim_y = 0, tb_dim_z = 0;
- unsigned shmem = 0, nregs = 0, cuda_stream_id = 0, kernel_id = 0,
- binary_verion = 0;
- std::string line;
- std::stringstream ss;
- std::string string1, string2;
- std::string kernel_name;
-
- while (!ifs.eof()) {
- getline(ifs, line);
-
- if (line.length() == 0) {
- continue;
- } else if (line[0] == '#') {
- // the trace format, ignore this and assume fixed format for now
- break; // the begin of the instruction stream
- } else if (line[0] == '-') {
- ss.str(line);
- ss.ignore();
- ss >> string1 >> string2;
- if (string1 == "kernel" && string2 == "name") {
- const size_t equal_idx = line.find('=');
- kernel_name = line.substr(equal_idx + 1);
- } else if (string1 == "kernel" && string2 == "id") {
- sscanf(line.c_str(), "-kernel id = %d", &kernel_id);
- } else if (string1 == "grid" && string2 == "dim") {
- sscanf(line.c_str(), "-grid dim = (%d,%d,%d)", &grid_dim_x, &grid_dim_y,
- &grid_dim_z);
- } else if (string1 == "block" && string2 == "dim") {
- sscanf(line.c_str(), "-block dim = (%d,%d,%d)", &tb_dim_x, &tb_dim_y,
- &tb_dim_z);
- } else if (string1 == "shmem") {
- sscanf(line.c_str(), "-shmem = %d", &shmem);
- } else if (string1 == "nregs") {
- sscanf(line.c_str(), "-nregs = %d", &nregs);
- } else if (string1 == "cuda" && string2 == "stream") {
- sscanf(line.c_str(), "-cuda stream id = %d", &cuda_stream_id);
- } else if (string1 == "binary" && string2 == "version") {
- sscanf(line.c_str(), "-binary version = %d", &binary_verion);
- }
- std::cout << line << std::endl;
- continue;
- }
- }
-
- gpgpu_ptx_sim_info info;
- info.smem = shmem;
- info.regs = nregs;
- dim3 gridDim(grid_dim_x, grid_dim_y, grid_dim_z);
- dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z);
- trace_function_info* function_info =
- new trace_function_info(info, m_gpgpu_context);
- function_info->set_name(kernel_name.c_str());
- trace_kernel_info_t* kernel_info =
- new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info,
- &ifs, m_gpgpu_sim, m_gpgpu_context, config);
-
- return kernel_info;
-}
-
-void trace_parser::kernel_finalizer(trace_kernel_info_t* kernel_info) {
- if (ifs.is_open()) ifs.close();
-
- delete kernel_info->entry();
- delete kernel_info;
-}
-
-const trace_warp_inst_t* trace_shd_warp_t::get_next_trace_inst() {
- if (trace_pc < warp_traces.size()) {
- return &warp_traces[trace_pc++];
- } else
- return NULL;
-}
-
-void trace_shd_warp_t::clear() {
- trace_pc = 0;
- warp_traces.clear();
-}
-
-// functional_done
-bool trace_shd_warp_t::trace_done() { return trace_pc == (warp_traces.size()); }
-
-address_type trace_shd_warp_t::get_start_trace_pc() {
- assert(warp_traces.size() > 0);
- return warp_traces[0].pc;
-}
-
-address_type trace_shd_warp_t::get_pc() {
- assert(warp_traces.size() > 0);
- assert(trace_pc < warp_traces.size());
- return warp_traces[trace_pc].pc;
-}
-
-trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim,
- unsigned m_binary_verion,
- trace_function_info* m_function_info,
- std::ifstream* inputstream,
- gpgpu_sim* gpgpu_sim,
- gpgpu_context* gpgpu_context,
- class trace_config* config)
- : kernel_info_t(gridDim, blockDim, m_function_info) {
- ifs = inputstream;
- m_gpgpu_sim = gpgpu_sim;
- m_gpgpu_context = gpgpu_context;
- binary_verion = m_binary_verion;
- m_tconfig = config;
-
- // resolve the binary version
- if (m_binary_verion == VOLTA_BINART_VERSION)
- OpcodeMap = &Volta_OpcodeMap;
- else if (m_binary_verion == PASCAL_TITANX_BINART_VERSION ||
- m_binary_verion == PASCAL_P100_BINART_VERSION)
- OpcodeMap = &Pascal_OpcodeMap;
- else if (m_binary_verion == KEPLER_BINART_VERSION)
- OpcodeMap = &Kepler_OpcodeMap;
- else if (m_binary_verion == TURING_BINART_VERSION)
- OpcodeMap = &Turing_OpcodeMap;
- else
- assert(0 && "unsupported binary version");
-}
-
-bool trace_kernel_info_t::get_next_threadblock_traces(
- std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces) {
- for (unsigned i = 0; i < threadblock_traces.size(); ++i) {
- threadblock_traces[i]->clear();
- }
-
- unsigned block_id_x = 0, block_id_y = 0, block_id_z = 0;
- unsigned warp_id = 0;
- unsigned insts_num = 0;
-
- bool start_of_tb_stream_found = false;
-
- while (!ifs->eof()) {
- std::string line;
- std::stringstream ss;
- std::string string1, string2;
-
- getline(*ifs, line);
-
- if (line.length() == 0) {
- continue;
- } else {
- ss.str(line);
- ss >> string1 >> string2;
- if (string1 == "#BEGIN_TB") {
- if (!start_of_tb_stream_found) {
- start_of_tb_stream_found = true;
- } else
- assert(0 &&
- "Parsing error: thread block start before the previous one "
- "finish");
- } else if (string1 == "#END_TB") {
- assert(start_of_tb_stream_found);
- break; // end of TB stream
- } else if (string1 == "thread" && string2 == "block") {
- assert(start_of_tb_stream_found);
- sscanf(line.c_str(), "thread block = %d,%d,%d", &block_id_x,
- &block_id_y, &block_id_z);
- std::cout << line << std::endl;
- } else if (string1 == "warp") {
- // the start of new warp stream
- assert(start_of_tb_stream_found);
- sscanf(line.c_str(), "warp = %d", &warp_id);
- } else if (string1 == "insts") {
- assert(start_of_tb_stream_found);
- sscanf(line.c_str(), "insts = %d", &insts_num);
- threadblock_traces[warp_id]->reserve(insts_num);
- } else {
- assert(start_of_tb_stream_found);
- trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(),
- m_gpgpu_context, m_tconfig);
- inst.parse_from_string(line, OpcodeMap);
- threadblock_traces[warp_id]->push_back(inst);
- }
- }
- }
-
- return true;
-}
-
-bool trace_warp_inst_t::check_opcode_contain(
- const std::vector<std::string>& opcode, std::string param) {
- for (unsigned i = 0; i < opcode.size(); ++i)
- if (opcode[i] == param) return true;
-
- return false;
-}
-
-unsigned trace_warp_inst_t::get_datawidth_from_opcode(
- const std::vector<std::string>& opcode) {
- for (unsigned i = 0; i < opcode.size(); ++i) {
- if (is_number(opcode[i])) {
- return (std::stoi(opcode[i], NULL) / 8);
- } else if (opcode[i][0] == 'U' && is_number(opcode[i].substr(1))) {
- // handle the U* case
- unsigned bits;
- sscanf(opcode[i].c_str(), "U%u", &bits);
- return bits / 8;
- }
- }
-
- return 4; // default is 4 bytes
-}
-
-bool trace_warp_inst_t::parse_from_string(
- std::string trace,
- const std::unordered_map<std::string, OpcodeChar>* OpcodeMap) {
- std::stringstream ss;
- ss.str(trace);
-
- std::string temp;
- unsigned threadblock_x = 0, threadblock_y = 0, threadblock_z = 0,
- warpid_tb = 0, sm_id = 0, warpid_sm = 0;
- unsigned long long m_pc = 0;
- unsigned mask = 0;
- unsigned reg_dest[4];
- std::string opcode;
- unsigned reg_dsts_num = 0;
- unsigned reg_srcs_num = 0;
- unsigned reg_srcs[4];
- unsigned mem_width = 0;
- unsigned long long mem_addresses[warp_size()];
- unsigned address_mode = 0;
- unsigned long long base_address = 0;
- int stride = 0;
-
- // Start Parsing
- ss >> std::dec >> threadblock_x >> threadblock_y >> threadblock_z >>
- warpid_tb;
-
- // ignore core id
- // ss>>std::dec>>sm_id>>warpid_sm;
-
- ss >> std::hex >> m_pc;
- ss >> std::hex >> mask;
-
- std::bitset<MAX_WARP_SIZE> mask_bits(mask);
-
- ss >> std::dec >> reg_dsts_num;
- for (unsigned i = 0; i < reg_dsts_num; ++i) {
- ss >> std::dec >> temp;
- sscanf(temp.c_str(), "R%d", &reg_dest[i]);
- }
-
- ss >> opcode;
-
- ss >> reg_srcs_num;
- for (unsigned i = 0; i < reg_srcs_num; ++i) {
- ss >> temp;
- sscanf(temp.c_str(), "R%d", &reg_srcs[i]);
- }
-
- ss >> mem_width;
-
- if (mem_width > 0) // then it is a memory inst
- {
- ss >> std::dec >> address_mode;
- if (address_mode == 0) {
- // read addresses one by one from the file
- for (int s = 0; s < warp_size(); s++) {
- if (mask_bits.test(s))
- ss >> std::hex >> mem_addresses[s];
- else
- mem_addresses[s] = 0;
- }
- } else if (address_mode == 1) {
- // read addresses as base address and stride
- ss >> std::hex >> base_address;
- ss >> std::dec >> stride;
- bool first_bit1_found = false;
- bool last_bit1_found = false;
- unsigned long long addra = base_address;
- for (int s = 0; s < warp_size(); s++) {
- if (mask_bits.test(s) && !first_bit1_found) {
- first_bit1_found = true;
- mem_addresses[s] = base_address;
- } else if (first_bit1_found && !last_bit1_found) {
- if (mask_bits.test(s)) {
- addra += stride;
- mem_addresses[s] = addra;
- } else
- last_bit1_found = true;
- } else
- mem_addresses[s] = 0;
- }
- }
- }
- // Finish Parsing
- // After parsing, fill the inst_t and warp_inst_t params
-
- // fill active mask
- active_mask_t active_mask = mask_bits;
- set_active(active_mask);
-
- // get the opcode
- std::istringstream iss(opcode);
- std::vector<std::string> opcode_tokens;
- std::string token;
- while (std::getline(iss, token, '.')) {
- if (!token.empty()) opcode_tokens.push_back(token);
- }
-
- std::string opcode1 = opcode_tokens[0];
-
- // fill and initialize common params
- m_decoded = true;
- pc = (address_type)m_pc; // we will lose the high 32 bits from casting long
- // to unsigned, it should be okay!
-
- isize =
- 16; // starting from MAXWELL isize=16 bytes (including the control bytes)
- for (unsigned i = 0; i < MAX_OUTPUT_VALUES; i++) {
- out[i] = 0;
- }
- for (unsigned i = 0; i < MAX_INPUT_VALUES; i++) {
- in[i] = 0;
- }
-
- is_vectorin = 0;
- is_vectorout = 0;
- ar1 = 0;
- ar2 = 0;
- memory_op = no_memory_op;
- data_size = 0;
- op = ALU_OP;
- mem_op = NOT_TEX;
-
- std::unordered_map<std::string, OpcodeChar>::const_iterator it =
- OpcodeMap->find(opcode1);
- if (it != OpcodeMap->end()) {
- m_opcode = it->second.opcode;
- op = (op_type)(it->second.opcode_category);
- } else {
- std::cout << "ERROR: undefined instruction : " << opcode
- << " Opcode: " << opcode1 << std::endl;
- assert(0 && "undefined instruction");
- }
-
- // fill regs information
- num_regs = reg_srcs_num + reg_dsts_num;
- num_operands = num_regs;
- outcount = reg_dsts_num;
- for (unsigned m = 0; m < reg_dsts_num; ++m) {
- out[m] = reg_dest[m] + 1; // Increment by one because GPGPU-sim starts from
- // R1, while SASS starts from R0
- arch_reg.dst[m] = reg_dest[m] + 1;
- }
-
- incount = reg_srcs_num;
- for (unsigned m = 0; m < reg_srcs_num; ++m) {
- in[m] = reg_srcs[m] + 1; // Increment by one because GPGPU-sim starts from
- // R1, while SASS starts from R0
- arch_reg.src[m] = reg_srcs[m] + 1;
- }
- // TO DO: handle: vector, store insts have no output, double inst and hmma,
- // and 64 bit address remove redundant registers
-
- // fill latency and initl
- m_tconfig->set_latency(op, latency, initiation_interval);
-
- // fill addresses
- if (mem_width > 0) {
- for (unsigned i = 0; i < warp_size(); ++i) set_addr(i, mem_addresses[i]);
- }
-
- // handle special cases and fill memory space
- switch (m_opcode) {
- case OP_LDG:
- case OP_LDL:
- assert(mem_width > 0);
- // Nvbit reports incorrect data width, and we have to parse the opcode to
- // get the correct data width
- data_size = get_datawidth_from_opcode(opcode_tokens);
- memory_op = memory_load;
- cache_op = CACHE_ALL;
- if (m_opcode == OP_LDL)
- space.set_type(local_space);
- else
- space.set_type(global_space);
- // check the cache scope, if its strong GPU, then bypass L1
- if (check_opcode_contain(opcode_tokens, "STRONG") &&
- check_opcode_contain(opcode_tokens, "GPU")) {
- cache_op = CACHE_GLOBAL;
- }
- break;
- case OP_STG:
- case OP_STL:
- case OP_ATOMG:
- case OP_RED:
- case OP_ATOM:
- assert(mem_width > 0);
- data_size = get_datawidth_from_opcode(opcode_tokens);
- memory_op = memory_store;
- cache_op = CACHE_ALL;
- if (m_opcode == OP_STL)
- space.set_type(local_space);
- else
- space.set_type(global_space);
-
- if (m_opcode == OP_ATOMG || m_opcode == OP_ATOM || m_opcode == OP_RED) {
- m_isatomic = true;
- memory_op = memory_load;
- op = LOAD_OP;
- cache_op = CACHE_GLOBAL;
-
- // ATOMIC writes to the first operand, we missed that in the trace so we
- // fixed it here. TO be fixed in tracer
- outcount = reg_dsts_num + 1;
- out[0] = in[0]; // Increment by one because GPGPU-sim starts from R1,
- // while SASS starts from R0
- arch_reg.dst[0] = reg_srcs[0];
- num_regs = reg_srcs_num + reg_dsts_num + 1;
- num_operands = num_regs;
- }
-
- break;
- case OP_LDS:
- case OP_STS:
- case OP_ATOMS:
- assert(mem_width > 0);
- data_size = mem_width;
- space.set_type(shared_space);
- if (m_opcode == OP_ATOMS || m_opcode == OP_LDS) {
- // m_isatomic = true;
- op = LOAD_OP;
- memory_op = memory_load;
- }
- break;
- case OP_ST:
- case OP_LD:
- // TO DO: set generic load based on the address
- // right now, we consider all loads are shared.
- assert(mem_width > 0);
- data_size = get_datawidth_from_opcode(opcode_tokens);
- space.set_type(shared_space);
- if (m_opcode == OP_LD)
- memory_op = memory_load;
- else
- memory_op = memory_store;
- break;
- case OP_BAR:
- // TO DO: fill this correctly
- bar_id = 0;
- bar_count = (unsigned)-1;
- bar_type = SYNC;
- // TO DO
- // if bar_type = RED;
- // set bar_type
- // barrier_type bar_type;
- // reduction_type red_type;
- break;
- case OP_HADD2:
- case OP_HADD2_32I:
- case OP_HFMA2:
- case OP_HFMA2_32I:
- case OP_HMUL2_32I:
- case OP_HSET2:
- case OP_HSETP2:
- initiation_interval =
- initiation_interval / 2; // FP16 has 2X throughput than FP32
- break;
- default:
- break;
- }
-
- return true;
-}
-
-trace_config::trace_config() {}
-
-void trace_config::reg_options(option_parser_t opp) {
- option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename,
- "traces kernel file"
- "traces kernel file directory",
- "./traces/kernelslist.g");
-
- option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR,
- &trace_opcode_latency_initiation_int,
- "Opcode latencies and initiation for integers in "
- "trace driven mode <latency,initiation>",
- "4,1");
- option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR,
- &trace_opcode_latency_initiation_sp,
- "Opcode latencies and initiation for sp in trace "
- "driven mode <latency,initiation>",
- "4,1");
- option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR,
- &trace_opcode_latency_initiation_dp,
- "Opcode latencies and initiation for dp in trace "
- "driven mode <latency,initiation>",
- "4,1");
- option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR,
- &trace_opcode_latency_initiation_sfu,
- "Opcode latencies and initiation for sfu in trace "
- "driven mode <latency,initiation>",
- "4,1");
- option_parser_register(opp, "-trace_opcode_latency_initiation_tensor",
- OPT_CSTR, &trace_opcode_latency_initiation_tensor,
- "Opcode latencies and initiation for tensor in trace "
- "driven mode <latency,initiation>",
- "4,1");
-
- for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) {
- std::stringstream ss;
- ss << "-trace_opcode_latency_initiation_spec_op_" << j + 1;
- option_parser_register(opp, ss.str().c_str(), OPT_CSTR,
- &trace_opcode_latency_initiation_specialized_op[j],
- "specialized unit config"
- " <latency,initiation>",
- "4,4");
- }
-}
-
-void trace_config::parse_config() {
- sscanf(trace_opcode_latency_initiation_int, "%u,%u", &int_latency, &int_init);
- sscanf(trace_opcode_latency_initiation_sp, "%u,%u", &fp_latency, &fp_init);
- sscanf(trace_opcode_latency_initiation_dp, "%u,%u", &dp_latency, &dp_init);
- sscanf(trace_opcode_latency_initiation_sfu, "%u,%u", &sfu_latency, &sfu_init);
- sscanf(trace_opcode_latency_initiation_tensor, "%u,%u", &tensor_latency,
- &tensor_init);
-
- for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) {
- sscanf(trace_opcode_latency_initiation_specialized_op[j], "%u,%u",
- &specialized_unit_latency[j], &specialized_unit_initiation[j]);
- }
-}
-void trace_config::set_latency(unsigned category, unsigned& latency,
- unsigned& initiation_interval) {
- initiation_interval = latency = 1;
-
- switch (category) {
- case ALU_OP:
- case INTP_OP:
- case BRANCH_OP:
- case CALL_OPS:
- case RET_OPS:
- latency = int_latency;
- initiation_interval = int_init;
- break;
- case SP_OP:
- latency = fp_latency;
- initiation_interval = fp_init;
- break;
- case DP_OP:
- latency = dp_latency;
- initiation_interval = dp_init;
- break;
- case SFU_OP:
- latency = sfu_latency;
- initiation_interval = sfu_init;
- break;
- case TENSOR_CORE_OP:
- latency = tensor_latency;
- initiation_interval = tensor_init;
- break;
- default:
- break;
- }
- // for specialized units
- if (category >= SPEC_UNIT_START_ID) {
- unsigned spec_id = category - SPEC_UNIT_START_ID;
- assert(spec_id >= 0 && spec_id < SPECIALIZED_UNIT_NUM);
- latency = specialized_unit_latency[spec_id];
- initiation_interval = specialized_unit_initiation[spec_id];
- }
-}
-
-void trace_gpgpu_sim::createSIMTCluster() {
- m_cluster = new simt_core_cluster*[m_shader_config->n_simt_clusters];
- for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++)
- m_cluster[i] =
- new trace_simt_core_cluster(this, i, m_shader_config, m_memory_config,
- m_shader_stats, m_memory_stats);
-}
-
-void trace_simt_core_cluster::create_shader_core_ctx() {
- m_core = new shader_core_ctx*[m_config->n_simt_cores_per_cluster];
- for (unsigned i = 0; i < m_config->n_simt_cores_per_cluster; i++) {
- unsigned sid = m_config->cid_to_sid(i, m_cluster_id);
- m_core[i] = new trace_shader_core_ctx(m_gpu, this, sid, m_cluster_id,
- m_config, m_mem_config, m_stats);
- m_core_sim_order.push_back(i);
- }
-}
-
-void trace_shader_core_ctx::create_shd_warp() {
- m_warp.resize(m_config->max_warps_per_shader);
- for (unsigned k = 0; k < m_config->max_warps_per_shader; ++k) {
- m_warp[k] = new trace_shd_warp_t(this, m_config->warp_size);
- }
-}
-
-void trace_shader_core_ctx::get_pdom_stack_top_info(unsigned warp_id,
- const warp_inst_t* pI,
- unsigned* pc,
- unsigned* rpc) {
- // In trace-driven mode, we assume no control hazard
- *pc = pI->pc;
- *rpc = pI->pc;
-}
-
-const active_mask_t& trace_shader_core_ctx::get_active_mask(
- unsigned warp_id, const warp_inst_t* pI) {
- // For Trace-driven, the active mask already set in traces, so
- // just read it from the inst
- return pI->get_active_mask();
-}
-
-unsigned trace_shader_core_ctx::sim_init_thread(
- kernel_info_t& kernel, ptx_thread_info** thread_info, int sid, unsigned tid,
- unsigned threads_left, unsigned num_threads, core_t* core,
- unsigned hw_cta_id, unsigned hw_warp_id, gpgpu_t* gpu) {
- if (kernel.no_more_ctas_to_run()) {
- return 0; // finished!
- }
-
- if (kernel.more_threads_in_cta()) {
- kernel.increment_thread_id();
- }
-
- if (!kernel.more_threads_in_cta()) kernel.increment_cta_id();
-
- return 1;
-}
-
-void trace_shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread,
- unsigned end_thread, unsigned ctaid,
- int cta_size, kernel_info_t& kernel) {
- // call base class
- shader_core_ctx::init_warps(cta_id, start_thread, end_thread, ctaid, cta_size,
- kernel);
-
- // then init traces
- unsigned start_warp = start_thread / m_config->warp_size;
- unsigned end_warp = end_thread / m_config->warp_size +
- ((end_thread % m_config->warp_size) ? 1 : 0);
-
- init_traces(start_warp, end_warp, kernel);
-}
-
-const warp_inst_t* trace_shader_core_ctx::get_next_inst(unsigned warp_id,
- address_type pc) {
- // read the inst from the traces
- trace_shd_warp_t* m_trace_warp =
- static_cast<trace_shd_warp_t*>(m_warp[warp_id]);
- return m_trace_warp->get_next_trace_inst();
-}
-
-void trace_shader_core_ctx::updateSIMTStack(unsigned warpId,
- warp_inst_t* inst) {
- // No SIMT-stack in trace-driven mode
-}
-
-void trace_shader_core_ctx::init_traces(unsigned start_warp, unsigned end_warp,
- kernel_info_t& kernel) {
- std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces;
- for (unsigned i = start_warp; i < end_warp; ++i) {
- trace_shd_warp_t* m_trace_warp = static_cast<trace_shd_warp_t*>(m_warp[i]);
- m_trace_warp->clear();
- threadblock_traces.push_back(&(m_trace_warp->warp_traces));
- }
- trace_kernel_info_t& trace_kernel = static_cast<trace_kernel_info_t&>(kernel);
- trace_kernel.get_next_threadblock_traces(threadblock_traces);
-
- // set the pc from the traces and ignore the functional model
- for (unsigned i = start_warp; i < end_warp; ++i) {
- trace_shd_warp_t* m_trace_warp = static_cast<trace_shd_warp_t*>(m_warp[i]);
- m_trace_warp->set_next_pc(m_trace_warp->get_start_trace_pc());
- }
-}
-
-void trace_shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t& inst,
- unsigned t,
- unsigned tid) {
- if (inst.isatomic()) m_warp[inst.warp_id()]->inc_n_atomic();
-
- if (inst.op == EXIT_OPS) {
- m_warp[inst.warp_id()]->set_completed(t);
- }
-}
-
-void trace_shader_core_ctx::func_exec_inst(warp_inst_t& inst) {
- // here, we generate memory acessess and set the status if thread (done?)
- if (inst.is_load() || inst.is_store()) {
- inst.generate_mem_accesses();
- }
- for (unsigned t = 0; t < m_warp_size; t++) {
- if (inst.active(t)) {
- unsigned warpId = inst.warp_id();
- unsigned tid = m_warp_size * warpId + t;
-
- // virtual function
- checkExecutionStatusAndUpdate(inst, t, tid);
- }
- }
- trace_shd_warp_t* m_trace_warp =
- static_cast<trace_shd_warp_t*>(m_warp[inst.warp_id()]);
- if (m_trace_warp->trace_done() && m_trace_warp->functional_done()) {
- m_trace_warp->ibuffer_flush();
- m_barriers.warp_exit(inst.warp_id());
- }
-}
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
deleted file mode 100644
index 3af99c3..0000000
--- a/src/trace-driven/trace_driven.h
+++ /dev/null
@@ -1,210 +0,0 @@
-// developed by Mahmoud Khairy, Purdue Univ
-
-#include <assert.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#ifndef TRACE_DRIVEN_H
-#define TRACE_DRIVEN_H
-
-#include "../abstract_hardware_model.h"
-#include "../gpgpu-sim/shader.h"
-#include "ISA_Def/trace_opcode.h"
-
-class trace_function_info : public function_info {
- public:
- trace_function_info(const struct gpgpu_ptx_sim_info& info,
- gpgpu_context* m_gpgpu_context)
- : function_info(0, m_gpgpu_context) {
- m_kernel_info = info;
- }
-
- virtual const struct gpgpu_ptx_sim_info* get_kernel_info() const {
- return &m_kernel_info;
- }
-
- virtual const void set_kernel_info(const struct gpgpu_ptx_sim_info& info) {
- m_kernel_info = info;
- }
-
- virtual ~trace_function_info() {}
-};
-
-class trace_warp_inst_t : public warp_inst_t {
- public:
- trace_warp_inst_t() {
- m_gpgpu_context = NULL;
- m_opcode = 0;
- m_tconfig = NULL;
- should_do_atomic = false;
- }
-
- trace_warp_inst_t(const class core_config* config,
- gpgpu_context* gpgpu_context, class trace_config* tconfig)
- : warp_inst_t(config) {
- m_gpgpu_context = gpgpu_context;
- m_opcode = 0;
- m_tconfig = tconfig;
- should_do_atomic = false;
- }
-
- bool parse_from_string(
- std::string trace,
- const std::unordered_map<std::string, OpcodeChar>* OpcodeMap);
-
- private:
- gpgpu_context* m_gpgpu_context;
- class trace_config* m_tconfig;
- unsigned m_opcode;
- bool check_opcode_contain(const std::vector<std::string>& opcode,
- std::string param);
- unsigned get_datawidth_from_opcode(const std::vector<std::string>& opcode);
-};
-
-class trace_kernel_info_t : public kernel_info_t {
- public:
- trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion,
- trace_function_info* m_function_info,
- std::ifstream* inputstream, gpgpu_sim* gpgpu_sim,
- gpgpu_context* gpgpu_context, class trace_config* config);
-
- bool get_next_threadblock_traces(
- std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces);
-
- private:
- std::ifstream* ifs;
- gpgpu_sim* m_gpgpu_sim;
- gpgpu_context* m_gpgpu_context;
- trace_config* m_tconfig;
- unsigned binary_verion;
- const std::unordered_map<std::string, OpcodeChar>* OpcodeMap;
-};
-
-class trace_config {
- public:
- trace_config();
-
- void set_latency(unsigned category, unsigned& latency,
- unsigned& initiation_interval);
- void parse_config();
- void reg_options(option_parser_t opp);
- char* get_traces_filename() { return g_traces_filename; }
-
- private:
- unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency;
- unsigned int_init, fp_init, dp_init, sfu_init, tensor_init;
- unsigned specialized_unit_latency[SPECIALIZED_UNIT_NUM];
- unsigned specialized_unit_initiation[SPECIALIZED_UNIT_NUM];
-
- char* g_traces_filename;
- char* trace_opcode_latency_initiation_int;
- char* trace_opcode_latency_initiation_sp;
- char* trace_opcode_latency_initiation_dp;
- char* trace_opcode_latency_initiation_sfu;
- char* trace_opcode_latency_initiation_tensor;
- char* trace_opcode_latency_initiation_specialized_op[SPECIALIZED_UNIT_NUM];
-};
-
-class trace_parser {
- public:
- trace_parser(const char* kernellist_filepath, gpgpu_sim* m_gpgpu_sim,
- gpgpu_context* m_gpgpu_context);
-
- std::vector<std::string> parse_kernellist_file();
- trace_kernel_info_t* parse_kernel_info(
- const std::string& kerneltraces_filepath, trace_config* config);
- void parse_memcpy_info(const std::string& memcpy_command, size_t& add,
- size_t& count);
-
- void kernel_finalizer(trace_kernel_info_t* kernel_info);
-
- private:
- std::string kernellist_filename;
- std::ifstream ifs;
- gpgpu_sim* m_gpgpu_sim;
- gpgpu_context* m_gpgpu_context;
-};
-
-class trace_shd_warp_t : public shd_warp_t {
- public:
- trace_shd_warp_t(class shader_core_ctx* shader, unsigned warp_size)
- : shd_warp_t(shader, warp_size) {
- trace_pc = 0;
- }
-
- std::vector<trace_warp_inst_t> warp_traces;
- const trace_warp_inst_t* get_next_trace_inst();
- void clear();
- bool trace_done();
- address_type get_start_trace_pc();
- virtual address_type get_pc();
-
- private:
- unsigned trace_pc;
-};
-
-class trace_gpgpu_sim : public gpgpu_sim {
- public:
- trace_gpgpu_sim(const gpgpu_sim_config& config, gpgpu_context* ctx)
- : gpgpu_sim(config, ctx) {
- createSIMTCluster();
- }
-
- virtual void createSIMTCluster();
-};
-
-class trace_simt_core_cluster : public simt_core_cluster {
- public:
- trace_simt_core_cluster(class gpgpu_sim* gpu, unsigned cluster_id,
- const shader_core_config* config,
- const memory_config* mem_config,
- class shader_core_stats* stats,
- class memory_stats_t* mstats)
- : simt_core_cluster(gpu, cluster_id, config, mem_config, stats, mstats) {
- create_shader_core_ctx();
- }
-
- virtual void create_shader_core_ctx();
-};
-
-class trace_shader_core_ctx : public shader_core_ctx {
- public:
- trace_shader_core_ctx(class gpgpu_sim* gpu, class simt_core_cluster* cluster,
- unsigned shader_id, unsigned tpc_id,
- const shader_core_config* config,
- const memory_config* mem_config,
- shader_core_stats* stats)
- : shader_core_ctx(gpu, cluster, shader_id, tpc_id, config, mem_config,
- stats) {
- create_front_pipeline();
- create_shd_warp();
- create_schedulers();
- create_exec_pipeline();
- }
-
- virtual void checkExecutionStatusAndUpdate(warp_inst_t& inst, unsigned t,
- unsigned tid);
- virtual void init_warps(unsigned cta_id, unsigned start_thread,
- unsigned end_thread, unsigned ctaid, int cta_size,
- kernel_info_t& kernel);
- virtual void func_exec_inst(warp_inst_t& inst);
- virtual unsigned sim_init_thread(kernel_info_t& kernel,
- ptx_thread_info** thread_info, int sid,
- unsigned tid, unsigned threads_left,
- unsigned num_threads, core_t* core,
- unsigned hw_cta_id, unsigned hw_warp_id,
- gpgpu_t* gpu);
- virtual void create_shd_warp();
- virtual const warp_inst_t* get_next_inst(unsigned warp_id, address_type pc);
- virtual void updateSIMTStack(unsigned warpId, warp_inst_t* inst);
- virtual void get_pdom_stack_top_info(unsigned warp_id, const warp_inst_t* pI,
- unsigned* pc, unsigned* rpc);
- virtual const active_mask_t& get_active_mask(unsigned warp_id,
- const warp_inst_t* pI);
-
- private:
- void init_traces(unsigned start_warp, unsigned end_warp,
- kernel_info_t& kernel);
-};
-
-#endif
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 21:24:04 +0000