diff options
44 files changed, 1952 insertions, 683 deletions
@@ -56,3 +56,8 @@ debug_tools/WatchYourStep/ptxjitplus/gpgpu* debug_tools/WatchYourStep/ptxjitplus/*.old debug_tools/WatchYourStep/ptxjitplus/ptxjitplus debug_tools/WatchYourStep/ptxjitplus/*.ptx + +# Accel-sim packages used for regressions +accel-sim-framework/ +gpu-app-collection/ + diff --git a/.travis.yml b/.travis.yml index 82f0604..2c75e69 100644 --- a/.travis.yml +++ b/.travis.yml @@ -13,15 +13,26 @@ matrix: - CONFIG=GTX480 - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - GPUAPPS_ROOT=/home/runner/gpgpu-sim_simulations/benchmarks - services: docker env: - CONFIG=TITANV - CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ + - GPUAPPS_ROOT=/home/runner/gpgpu-sim_simulations/benchmarks - services: docker env: - CONFIG=TITANV-LOCALXBAR - CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ + - GPUAPPS_ROOT=/home/runner/gpgpu-sim_simulations/benchmarks -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:volta_update /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -C $CONFIG -B rodinia_2.0-ft -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: + - > + docker run + --env CONFIG=$CONFIG + --env PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH + --env CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH + --env GPUAPPS_ROOT=$GPUAPPS_ROOT + -v `pwd`:/gpgpu-sim:rw tgrogers/gpgpu-sim_regress:volta_update + /bin/bash travis.sh diff --git a/Jenkinsfile b/Jenkinsfile index 4495461..a3db3e5 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -11,7 +11,7 @@ pipeline { stage('formatting-check') { steps { sh ''' - source /home/tgrogers-raid/a/common/gpgpu-sim-setup/common/export_gcc_version.sh 5.3.0 + source ./env-setup/common/export_gcc_version.sh 5.3.0 git remote add upstream https://github.com/purdue-aalp/gpgpu-sim_distribution git fetch upstream if git diff --name-only upstream/dev | grep -E "*.cc|*.h|*.cpp|*.hpp" ; then @@ -21,17 +21,18 @@ pipeline { } } */ + stage('env-setup') { + steps { + sh 'rm -rf env-setup && git clone [email protected]:purdue-aalp/env-setup.git &&\ + cd env-setup && git checkout cluster-ubuntu' + } + } stage('simulator-build') { steps { - parallel "4.2": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - make -j 10' - }, "10.1" : { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/10.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - make -j 10' - } + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + source `pwd`/setup_environment + make -j 10''' } } stage('simulations-build'){ @@ -41,36 +42,23 @@ pipeline { cd gpgpu-sim_simulations && \ git pull && \ ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - cd gpgpu-sim_simulations && \ - source ./benchmarks/src/setup_environment && \ - make -j 10 -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \ - make -C ./benchmarks/src data' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/10.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - cd gpgpu-sim_simulations && \ - source ./benchmarks/src/setup_environment && \ - make -j 10 -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ - make -C ./benchmarks/src data' + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + source `pwd`/setup_environment + cd gpgpu-sim_simulations + source ./benchmarks/src/setup_environment + make -j 10 -C ./benchmarks/src/ rodinia_2.0-ft + make -C ./benchmarks/src data''' } } - stage('regress'){ + stage('11.0 Regressions'){ steps { - parallel "4.2-rodinia": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - export PTXAS_CUDA_INSTALL_PATH=/home/tgrogers-raid/a/common/cuda-10.1 &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANV-PTXPLUS -N regress-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-per-app-4.2.csv' - }, "10.1-functest": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/10.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANV -N regress-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/10.1" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-per-app-10.1.csv -N regress-$$' - } + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + source `pwd`/setup_environment + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C QV100 -N regress-$$ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/11.0" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-per-app-11.0.csv -N regress-$$''' } } stage('correlate-delta-and-archive') { @@ -78,20 +66,15 @@ pipeline { sh './gpgpu-sim_simulations/run_hw/get_hw_data.sh' sh 'rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html && rm -rf gpgpu-sim-results-repo && rm -rf ./gpgpu-sim_simulations/util/plotting/htmls' sh 'git clone [email protected]:purdue-aalp/gpgpu-sim-results-repo.git' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C TITANV-PTXPLUS -A > stats-per-kernel-4.2-ptxplus.csv' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/10.1_env_setup.sh &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft,sdk-4.2 -C TITANV -A > stats-per-kernel-10.1.csv' + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C QV100 -A > stats-per-kernel-11.0.csv''' sh 'if [ ! -d ./gpgpu-sim-results-repo/${JOB_NAME} ]; then mkdir -p ./gpgpu-sim-results-repo/${JOB_NAME}/ ; cp ./gpgpu-sim-results-repo/purdue-aalp/gpgpu-sim_distribution/dev/* ./gpgpu-sim-results-repo/${JOB_NAME}/ ; fi' - sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-app-4.2.csv,./stats-per-app-4.2.csv -R > per-app-merge-4.2.csv' - sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-app-10.1.csv,./stats-per-app-10.1.csv -R > per-app-merge-10.1.csv' + sh './gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-app-11.0.csv,./stats-per-app-11.0.csv -R > per-app-merge-11.0.csv' sh 'PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-4.2.csv -P cuda-4.2 &&\ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-10.1.csv -P cuda-10.1 &&\ - ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-kernel-4.2-ptxplus.csv,./stats-per-kernel-4.2-ptxplus.csv -R > per-kernel-merge-4.2-ptxplus.csv &&\ - ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-kernel-10.1.csv,./stats-per-kernel-10.1.csv -R > per-kernel-merge-10.1.csv &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c per-kernel-merge-4.2-ptxplus.csv -p cuda-4.2 | grep -B 1 "Correl=" | tee correl.4.2.txt &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c per-kernel-merge-10.1.csv -p cuda-10.1 | grep -B 1 "Correl=" | tee correl.10.1.txt &&\ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c per-app-merge-11.0.csv -P cuda-11.0 &&\ + ./gpgpu-sim_simulations/util/plotting/merge-stats.py -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-kernel-11.0.csv,./stats-per-kernel-11.0.csv -R > per-kernel-merge-11.0.csv &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -H ./gpgpu-sim_simulations/run_hw/QUADRO-V100/device-0/9.1/ -c per-kernel-merge-11.0.csv -p cuda-11.0 | grep -B 1 "Correl=" | tee correl.11.0.txt &&\ mkdir -p ./gpgpu-sim-results-repo/${JOB_NAME}/ && cp stats-per-*.csv ./gpgpu-sim-results-repo/${JOB_NAME}/ &&\ cd ./gpgpu-sim-results-repo &&\ git diff --quiet && git diff --staged --quiet || git commit -am "Jenkins automated checkin ${JOB_NAME} Build:${BUILD_NUMBER}" &&\ @@ -57,12 +57,12 @@ endif $(shell mkdir -p $(SIM_OBJ_FILES_DIR)/libcuda && echo "const char *g_gpgpusim_build_string=\"$(GPGPUSIM_BUILD)\";" > $(SIM_OBJ_FILES_DIR)/detailed_version) -LIBS = cuda-sim gpgpu-sim_uarch $(INTERSIM) gpgpusimlib +LIBS = cuda-sim gpgpu-sim_uarch $(INTERSIM) gpgpusimlib TARGETS = ifeq ($(shell uname),Linux) - TARGETS += $(SIM_LIB_DIR)/libcudart.so + TARGETS += $(SIM_LIB_DIR)/libcudart.so else # MAC TARGETS += $(SIM_LIB_DIR)/libcudart.dylib endif @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so -Wl,--version-script=linux-so-version.txt\ + g++ -shared -Wl,-soname,libcudart.so -Wl,--version-script=linux-so-version.txt\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ @@ -167,7 +167,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.2 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.2; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.10.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.10.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.10.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.10.1; fi - + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.11.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.11.0; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ @@ -207,6 +207,12 @@ cuda-sim: makedirs $(MAKE) -C ./src/cuda-sim/ depend $(MAKE) -C ./src/cuda-sim/ +TFLAGS = -std=c++0x -I$(CUDA_INSTALL_PATH)/include +ifneq ($(DEBUG),1) + TFLAGS += -O3 +endif +TFLAGS += -g3 -fPIC + gpgpu-sim_uarch: makedirs cuda-sim $(MAKE) -C ./src/gpgpu-sim/ depend $(MAKE) -C ./src/gpgpu-sim/ @@ -11,12 +11,12 @@ This version of GPGPU-Sim has been tested with CUDA version 4.2, Please see the copyright notice in the file COPYRIGHT distributed with this release in the same directory as this file. -If you use GPGPU-Sim in your research, please cite: +If you use GPGPU-Sim 4.0 in your research, please cite: -Ali Bakhoda, George Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt, -Analyzing CUDA Workloads Using a Detailed GPU Simulator, in IEEE International -Symposium on Performance Analysis of Systems and Software (ISPASS), Boston, MA, -April 19-21, 2009. +Mahmoud Khairy, Zhesheng Shen, Tor M. Aamodt, Timothy G Rogers. +Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling. +In proceedings of the 47th IEEE/ACM International Symposium on Computer Architecture (ISCA), +May 29 - June 3, 2020. If you use cuDNN and Pytorch support, the Checkpoint function or the Debigging tool for functional simulation error in GPGPU-Sim for your research, please cite: @@ -24,11 +24,6 @@ Jonathan Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth S Analyzing Machine Learning Workloads Using a Detailed GPU Simulator, arXiv:1811.08933, https://arxiv.org/abs/1811.08933 -If you use the memory system in GPGPU-Sim, or the Volta/Pascal models, -please cite: -Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers, -Exploring Modern GPU Memory System Design Challenges through Accurate Modeling, arXiv:1810.07269, -https://arxiv.org/abs/1810.07269 If you use the Tensor Core in GPGPU-Sim or CUTLASS Library for your research please cite: diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index 6f088ea..609a9ef 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -63,10 +63,10 @@ -gpgpu_shmem_size 49152 -gpgpu_shmem_sizeDefault 49152 -icnt_flit_size 40 --gmem_skip_L1D 0 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 35 --smem_latency 26 +-gpgpu_l1_latency 35 +-gpgpu_smem_latency 26 -gpgpu_flush_l1_cache 1 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -77,8 +77,8 @@ -gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 0 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4 -gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2 @@ -104,7 +104,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-gpgpu_l2_rop_latency 120 -dram_latency 100 # dram model config diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt new file mode 100644 index 0000000..2fe3b53 --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 38; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config new file mode 100644 index 0000000..c83159f --- /dev/null +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -0,0 +1,183 @@ +# This config models the KEPLER (TITAN) +# For more info about this card, see Nvidia White paper +# https://wr0.wr.inf.h-brs.de/wr/hardware/nodes3/nvidia/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 35 +-gpgpu_ignore_resources_limitation 1 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 + +# Compute Capability +-gpgpu_compute_capability_major 3 +-gpgpu_compute_capability_minor 5 + +# PTX execution-driven +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 +# SASS trace-driven mode execution +#-trace_driven_mode 1 + +# high level architecture configuration +-gpgpu_n_clusters 14 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Kepler clock domains +#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> +# Kepler NVIDIA TITAN clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_700_series +-gpgpu_clock_domains 837.0:837.0:837.0:1502.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 62 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB +## Kepler has 6 SP SIMD units, 4 DPs and 2 SFU units per SM. +# There is no INT unit in kepler +-gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12 +-gpgpu_num_sp_units 6 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,8,8,8,130 +-ptx_opcode_initiation_sfu 2 +-ptx_opcode_latency_sfu 200 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use kepler Coalsce arhitetecture +-gpgpu_coalesce_arch 35 + +## In Kepler, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 0 + +# Kepler TITAN has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# The defulat is to disable the L1 cache, unless cache modifieres are used +-gpgpu_cache:dl1 S:4:128:32,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:32,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_sizeDefault 49152 +-gpgpu_shmem_size_PrefL1 16384 +-gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Kepler P102 and only enabled for local memory +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 +-gpgpu_gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 +-gpgpu_l1_latency 82 +-smem_latency 24 +-gpgpu_flush_l1_cache 1 + +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 1.5MB L2 cache +-gpgpu_cache:dl2 S:32:128:16,L:B:m:L:P,A:256:64,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 8 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# interconnection +-network_mode 1 +-inter_config_file config_kepler_islip.icnt + +# memory partition latency config +-gpgpu_l2_rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 64 + +# for NVIDIA TITAN, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 2500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Kepler +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 391269e..5b243a5 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -13,6 +13,7 @@ -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 # Compute Capability -gpgpu_compute_capability_major 6 @@ -23,9 +24,8 @@ -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster -gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 +-gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 12 -gpgpu_n_sub_partition_per_mchannel 2 @@ -36,110 +36,107 @@ -gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 -gpgpu_occupancy_sm_number 62 # This implies a maximum of 32 warps/SM --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 16 +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 -gpgpu_simd_model 1 # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs -# There is no int unit in Pascal -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 1 - +## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. +# There is no INT unit in Pascal +-gpgpu_pipeline_widths 4,0,0,4,4,4,0,0,4,4,8 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV,SHFL" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 -ptx_opcode_latency_int 4,13,4,5,145,32 -ptx_opcode_initiation_int 1,1,1,1,4,4 --ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_latency_fp 4,13,4,4,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,8,8,8,130 -ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 +-ptx_opcode_latency_sfu 20 + +# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs +-gpgpu_sub_core_model 1 +# enable operand collector +# disable specialized operand collectors and use generic operand collectors instead +-gpgpu_enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# 16 register banks, 4 banks per subcore +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Pascal Coalsce arhitetecture +-gpgpu_coalesce_arch 61 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 -# latencies and cache configs are adopted from: -# https://arxiv.org/pdf/1804.06826.pdf +## L1/shared memory configuration # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB -# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_shmem_size 49152 --gpgpu_shmem_sizeDefault 49152 --gpgpu_shmem_size_PrefL1 49152 --gpgpu_shmem_size_PrefShared 49152 +-gpgpu_l1_banks 2 +-gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_sizeDefault 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 # By default, L1 cache is disabled in Pascal P102. # requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 --gmem_skip_L1D 1 +-gpgpu_gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 82 --smem_latency 24 +-gpgpu_l1_latency 82 +-gpgpu_smem_latency 24 -gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:256:64,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 1 --memory_partition_indexing 0 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 4 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 8 # 48 KB Tex # Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use Pascal Coalsce arhitetecture --gpgpu_coalesce_arch 61 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection -network_mode 1 -inter_config_file config_pascal_islip.icnt # memory partition latency config --rop_latency 120 +-gpgpu_l2_rop_latency 120 -dram_latency 100 # dram model config @@ -164,17 +161,8 @@ -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt new file mode 100644 index 0000000..eed1c34 --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/config_turing_islip.icnt @@ -0,0 +1,73 @@ +//52*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 2.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config new file mode 100644 index 0000000..6fe04ee --- /dev/null +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -0,0 +1,184 @@ +# This config models the Turing RTX 2060 +# For more info about turing architecture: +# 1- https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf +# 2- "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 75 + +# Device Limits +-gpgpu_stack_size_limit 1024 +-gpgpu_heap_size_limit 8388608 +-gpgpu_runtime_sync_depth_limit 2 +-gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 + +# Compute Capability +-gpgpu_compute_capability_major 7 +-gpgpu_compute_capability_minor 5 + +# PTX execution-driven +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 30 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# volta clock domains +#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> +-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 +# boost mode +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 +-gpgpu_registers_per_block 65536 +-gpgpu_occupancy_sm_number 75 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE +## Turing has 4 SP SIMD units, 4 INT units, 4 SFU units, 8 Tensor core units +## We need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,0,4,4,4,4,0,4,4,4,8,4,4 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_int_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 +-ptx_opcode_latency_tesnor 64 +-ptx_opcode_initiation_tensor 64 + +# Turing has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto +## In Turing, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 75 + +# Trung has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-gpgpu_sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-gpgpu_enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# turing has 8 banks dual-port, 4 schedulers, two banks per scheduler +# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# ** Optional parameter - Required when mshr_type==Texture Fifo +-gpgpu_adaptive_cache_config 0 +-gpgpu_l1_banks 4 +-gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_sizeDefault 65536 +-gpgpu_shmem_per_block 65536 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_n_cluster_ejection_buffer_size 32 +-gpgpu_l1_latency 20 +-gpgpu_smem_latency 20 +-gpgpu_flush_l1_cache 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 4 +# 128 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod +-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-gpgpu_perfect_inst_const_cache 1 + +# interconnection +#-network_mode 1 +#-inter_config_file config_turing_islip.icnt +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_arbiter_algo 1 +-icnt_flit_size 40 + +# memory partition latency config +-gpgpu_l2_rop_latency 160 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# Turing has GDDR6 +# http://monitorinsider.com/GDDR6.html +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 2 +-gpgpu_dram_burst_length 16 +-dram_data_command_freq_ratio 4 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing, scaled to 3500MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62: + CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4" + +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Volta +-power_simulation_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index 91ff0b4..c4818d1 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -13,18 +13,19 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 - # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 0 # Compute Capability -gpgpu_compute_capability_major 7 -gpgpu_compute_capability_minor 0 -# SASS execution (only supported with CUDA >= 4.0) +# PTX execution-driven -gpgpu_ptx_convert_to_ptxplus 0 -gpgpu_ptx_save_converted_ptxplus 0 @@ -36,8 +37,6 @@ # volta clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Volta NVIDIA TITANV clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1132.0:1132.0:1132.0:850.0 # boost mode # -gpgpu_clock_domains 1628.0:1628.0:1628.0:850.0 @@ -67,8 +66,6 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -ptx_opcode_latency_int 4,13,4,5,145,21 -ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 @@ -80,6 +77,34 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 +# Volta has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-gpgpu_sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-gpgpu_enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +# we increase #banks to 16 to mitigate the effect of Regisrer File Cache (RFC) which we do not implement in the current version +-gpgpu_num_reg_banks 16 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +## L1/shared memory configuration # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory @@ -87,67 +112,49 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 +-gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks --l1_banks 4 -#-mem_unit_ports 4 +-gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 +-gpgpu_l1_latency 20 +-gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 4 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 4 # 128 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 32 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# Volta has 8 banks, 4 schedulers, two banks per scheduler -# However, since we do not model register file cache (RFC), we increase the number of banks to 32 to -# resuce banks conflits, mitigate RFC impact, and matche the hardware performance. To Do: RFC --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_flit_size 40 +-icnt_arbiter_algo 1 # memory partition latency config --rop_latency 160 +-gpgpu_l2_rop_latency 160 -dram_latency 100 # dram model config @@ -174,22 +181,13 @@ CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" # HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 +-dram_dual_bus_interface 1 # select lower bits for bnkgrp to increase bnkgrp parallelism -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto +#-dram_seperate_write_queue_enable 1 +#-dram_write_queue_size 64:56:32 # stat collection -gpgpu_memlatency_stat 14 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index a77ab74..3fa51ee 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -13,7 +13,6 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 - # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 @@ -67,7 +66,7 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency except shfl) are adopted from +# Throughput (initiation latency) are adopted from # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -ptx_opcode_latency_int 4,13,4,5,145,32 -ptx_opcode_initiation_int 2,2,2,2,8,4 @@ -80,6 +79,33 @@ -ptx_opcode_latency_tesnor 64 -ptx_opcode_initiation_tensor 64 +# Volta has sub core model, in which each scheduler has its own register file and EUs +# i.e. schedulers are isolated +-gpgpu_sub_core_model 1 +# disable specialized operand collectors and use generic operand collectors instead +-gpgpu_enable_specialized_operand_collector 0 +-gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_in_ports_gen 8 +-gpgpu_operand_collector_num_out_ports_gen 8 +# volta has 8 banks, 4 schedulers, two banks per scheduler +-gpgpu_num_reg_banks 8 +-gpgpu_reg_file_port_throughput 2 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +# Volta has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Greedy then oldest scheduler +-gpgpu_scheduler gto +## In Volta, a warp scheduler can issue 1 inst per cycle +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +## L1/shared memory configuration # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory @@ -87,65 +113,49 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adaptive_cache_config 1 +-gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks --l1_banks 4 -#-mem_unit_ports 4 +-gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 +-gpgpu_gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 20 --smem_latency 20 +-gpgpu_l1_latency 20 +-gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache --gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 1 --memory_partition_indexing 4 +-gpgpu_perf_sim_memcpy 1 +-gpgpu_memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_inst_fetch_throughput 4 # 48 KB Tex # Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# Volta has sub core model, in which each scheduler has its own register file and EUs -# i.e. schedulers are isolated --sub_core_model 1 -# disable specialized operand collectors and use generic operand collectors instead --enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 --gpgpu_operand_collector_num_in_ports_gen 8 --gpgpu_operand_collector_num_out_ports_gen 8 -# volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 8 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Volta, a warp scheduler can issue 1 inst per cycle --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 +-gpgpu_perfect_inst_const_cache 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt -# for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt +# use built-in local xbar +-network_mode 2 +-icnt_in_buffer_limit 512 +-icnt_out_buffer_limit 512 +-icnt_subnets 2 +-icnt_flit_size 40 +-icnt_arbiter_algo 1 # memory partition latency config --rop_latency 160 +-gpgpu_l2_rop_latency 160 -dram_latency 100 # dram model config @@ -172,22 +182,13 @@ CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" # HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 +-dram_dual_bus_interface 1 # select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 +-dram_bnk_indexing_policy 1 -dram_bnkgrp_indexing_policy 1 -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Volta has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto +-dram_seperate_write_queue_enable 1 +-dram_write_queue_size 128:108:32 # stat collection -gpgpu_memlatency_stat 14 @@ -203,3 +204,4 @@ #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0 + diff --git a/format-code.sh b/format-code.sh index 39c24e4..fb1cc90 100755 --- a/format-code.sh +++ b/format-code.sh @@ -10,3 +10,6 @@ clang-format -i ${THIS_DIR}/src/cuda-sim/*.h clang-format -i ${THIS_DIR}/src/cuda-sim/*.cc clang-format -i ${THIS_DIR}/src/gpuwattch/*.h clang-format -i ${THIS_DIR}/src/gpuwattch/*.cc +clang-format -i ${THIS_DIR}/src/trace-driven/*.h +clang-format -i ${THIS_DIR}/src/trace-driven/*.cc +clang-format -i ${THIS_DIR}/src/trace-driven/ISA_Def/*.h diff --git a/linux-so-version.txt b/linux-so-version.txt index 45c40dd..3db07ac 100644 --- a/linux-so-version.txt +++ b/linux-so-version.txt @@ -8,5 +8,7 @@ libcudart.so.10.0{ }; libcudart.so.10.1{ }; +libcudart.so.11.0{ +}; libcuda.so.1{ }; diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index c841fb0..1c88551 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -13,11 +13,18 @@ pipeline { } stages { + stage('env-setup') { + steps { + sh 'rm -rf env-setup && git clone [email protected]:purdue-aalp/env-setup.git &&\ + cd env-setup && git checkout cluster-ubuntu' + } + } stage('nightly-simulator-build') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - make -j 10' + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + source `pwd`/setup_environment + make -j 10''' } } stage('nightly-simulations-build'){ @@ -30,12 +37,13 @@ pipeline { cd gpgpu-sim_simulations && \ git pull && \ ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ make -i -j 10 -C ./benchmarks/src/ all && \ - make -C ./benchmarks/src data' + make -C ./benchmarks/src data''' } } stage('nightly-2B-insn-run'){ @@ -43,13 +51,14 @@ pipeline { sh 'rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html && rm -rf gpgpu-sim-results-repo &&\ rm -rf ./gpgpu-sim_simulations/util/plotting/htmls' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh + source `pwd`/setup_environment ./gpgpu-sim_simulations/util/job_launching/run_simulations.py \ - -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/correlation-apps.list` -C QV100-2B -N nightly-$$ && \ + -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/correlation-apps.list` -C QV100-2B -N nightly-$$ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v \ - -s stats-per-app-9.1.csv -T 12 -K -N nightly-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-9.1.csv -P cuda-9.1.nightly' + -s stats-per-app-11.0.csv -T 12 -K -N nightly-$$ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-per-app-11.0.csv -P cuda-11.0.nightly''' } } stage('nightly-correlate'){ @@ -63,25 +72,26 @@ pipeline { fi && \ ./gpgpu-sim_simulations/run_hw/get_hw_data.sh' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + sh '''#!/bin/bash + source ./env-setup/11.0_env_setup.sh ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k \ -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/correlation-apps.list` \ - -C QV100-2B > stats-per-kernel-9.1.csv &&\ + -C QV100-2B > stats-per-kernel-11.0.csv ./gpgpu-sim_simulations/util/plotting/merge-stats.py \ - -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-app-9.1.csv,./stats-per-app-9.1.csv -R \ - > per-app-merge-9.1.csv &&\ + -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-app-11.0.csv,./stats-per-app-11.0.csv -R \ + > per-app-merge-11.0.csv ./gpgpu-sim_simulations/util/plotting/merge-stats.py \ - -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-kernel-9.1.csv,./stats-per-kernel-9.1.csv -R \ - > per-kernel-merge-9.1.csv &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c per-kernel-merge-9.1.csv \ - -p cuda-9.1.nightly -b ./gpgpu-sim_simulations/util/plotting/known.correlation.outliers.list \ - | grep "Correl=" -B 1 | tee correl.9.1.txt &&\ - cp stats-per-*.csv ./gpgpu-sim-results-repo/${JOB_NAME}/ &&\ - cd ./gpgpu-sim-results-repo &&\ - git pull &&\ - git diff --quiet && git diff --staged --quiet || git commit -am "Jenkins automated checkin ${JOB_NAME} Build:${BUILD_NUMBER}" &&\ - git push' + -c ./gpgpu-sim-results-repo/${JOB_NAME}/stats-per-kernel-11.0.csv,./stats-per-kernel-11.0.csv -R \ + > per-kernel-merge-11.0.csv + source `pwd`/setup_environment + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c per-kernel-merge-11.0.csv \ + -p cuda-11.0.nightly -b ./gpgpu-sim_simulations/util/plotting/known.correlation.outliers.list \ + | grep "Correl=" -B 1 | tee correl.11.0.txt + cp stats-per-*.csv ./gpgpu-sim-results-repo/${JOB_NAME}/ + cd ./gpgpu-sim-results-repo + git pull + git diff --quiet && git diff --staged --quiet || git commit -am "Jenkins automated checkin ${JOB_NAME} Build:${BUILD_NUMBER}" + git push''' sh 'PLOTDIR="/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/jenkins/${JOB_NAME}" &&\ ssh [email protected] mkdir -p $PLOTDIR/${BUILD_NUMBER} && \ diff --git a/setup_environment b/setup_environment index daf7fab..07d0788 100644 --- a/setup_environment +++ b/setup_environment @@ -48,7 +48,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; export CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 10100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 11100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; echo $CUDA_VERSION_NUMBER return diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 7922bc5..5ad6f10 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -257,6 +257,7 @@ void warp_inst_t::do_atomic(bool forceDo) { void warp_inst_t::do_atomic(const active_mask_t &access_mask, bool forceDo) { assert(m_isatomic && (!m_empty || forceDo)); + if (!should_do_atomic) return; for (unsigned i = 0; i < m_config->warp_size; i++) { if (access_mask.test(i)) { dram_callback_t &cb = m_per_scalar_thread[i].callback; @@ -536,13 +537,30 @@ void warp_inst_t::memory_coalescing_arch(bool is_write, transaction_info &info = subwarp_transactions[block_address]; // can only write to one segment - assert(block_address == line_size_based_tag_func( - addr + data_size_coales - 1, segment_size)); + // it seems like in trace driven, a thread can write to more than one + // segment assert(block_address == + // line_size_based_tag_func(addr+data_size_coales-1,segment_size)); info.chunks.set(chunk); info.active.set(thread); unsigned idx = (addr & 127); - for (unsigned i = 0; i < data_size_coales; i++) info.bytes.set(idx + i); + for (unsigned i = 0; i < data_size_coales; i++) + if ((idx + i) < MAX_MEMORY_ACCESS_SIZE) info.bytes.set(idx + i); + + // it seems like in trace driven, a thread can write to more than one + // segment handle this special case + if (block_address != line_size_based_tag_func( + addr + data_size_coales - 1, segment_size)) { + addr = addr + data_size_coales - 1; + unsigned block_address = line_size_based_tag_func(addr, segment_size); + unsigned chunk = (addr & 127) / 32; + transaction_info &info = subwarp_transactions[block_address]; + info.chunks.set(chunk); + info.active.set(thread); + unsigned idx = (addr & 127); + for (unsigned i = 0; i < data_size_coales; i++) + if ((idx + i) < MAX_MEMORY_ACCESS_SIZE) info.bytes.set(idx + i); + } } } @@ -746,6 +764,10 @@ kernel_info_t::kernel_info_t(dim3 gridDim, dim3 blockDim, // Jin: launch latency management m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency; + m_kernel_TB_latency = + entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency + + num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency; + cache_config_set = false; } @@ -773,6 +795,10 @@ kernel_info_t::kernel_info_t( // Jin: launch latency management m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency; + m_kernel_TB_latency = + entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency + + num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency; + cache_config_set = false; m_NameToCudaArray = nameToCudaArray; m_NameToTextureInfo = nameToTextureInfo; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c6e3b43..49f3e9f 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,7 +65,7 @@ enum FuncCache { FuncCachePreferL1 = 2 }; -enum AdaptiveCache { FIXED = 0, VOLTA = 1 }; +enum AdaptiveCache { FIXED = 0, ADAPTIVE_VOLTA = 1 }; #ifdef __cplusplus @@ -79,6 +79,8 @@ typedef unsigned address_type; typedef unsigned addr_t; // the following are operations the timing model can see +#define SPECIALIZED_UNIT_NUM 8 +#define SPEC_UNIT_START_ID 100 enum uarch_op_t { NO_OP = -1, @@ -97,7 +99,16 @@ enum uarch_op_t { BARRIER_OP, MEMORY_BARRIER_OP, CALL_OPS, - RET_OPS + RET_OPS, + EXIT_OPS, + SPECIALIZED_UNIT_1_OP = SPEC_UNIT_START_ID, + SPECIALIZED_UNIT_2_OP, + SPECIALIZED_UNIT_3_OP, + SPECIALIZED_UNIT_4_OP, + SPECIALIZED_UNIT_5_OP, + SPECIALIZED_UNIT_6_OP, + SPECIALIZED_UNIT_7_OP, + SPECIALIZED_UNIT_8_OP }; typedef enum uarch_op_t op_type; @@ -134,7 +145,8 @@ enum operation_pipeline_t { INTP__OP, SFU__OP, TENSOR_CORE__OP, - MEM__OP + MEM__OP, + SPECIALIZED__OP, }; typedef enum operation_pipeline_t operation_pipeline; enum mem_operation_t { NOT_TEX, TEX }; @@ -326,6 +338,9 @@ class kernel_info_t { unsigned m_launch_latency; mutable bool cache_config_set; + + unsigned m_kernel_TB_latency; // this used for any CPU-GPU kernel latency and + // counted in the gpu_cycle }; class core_config { @@ -618,6 +633,8 @@ class gpgpu_t { return m_NameToTextureInfo; } + virtual ~gpgpu_t() {} + protected: const gpgpu_functional_sim_config &m_function_model_config; FILE *ptx_inst_debug_file; @@ -993,6 +1010,7 @@ class warp_inst_t : public inst_t { m_cache_hit = false; m_is_printf = false; m_is_cdp = 0; + should_do_atomic = true; } virtual ~warp_inst_t() {} @@ -1141,6 +1159,7 @@ class warp_inst_t : public inst_t { unsigned long long issue_cycle; unsigned cycles; // used for implementing initiation interval delay bool m_isatomic; + bool should_do_atomic; bool m_is_printf; unsigned m_warp_id; unsigned m_dynamic_warp_id; @@ -1229,7 +1248,7 @@ class core_t { } void execute_warp_inst_t(warp_inst_t &inst, unsigned warpId = (unsigned)-1); bool ptx_thread_done(unsigned hw_thread_id) const; - void updateSIMTStack(unsigned warpId, warp_inst_t *inst); + virtual void updateSIMTStack(unsigned warpId, warp_inst_t *inst); void initilizeSIMTStack(unsigned warp_count, unsigned warps_size); void deleteSIMTStack(); warp_inst_t getExecuteWarp(unsigned warpId); diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index 1d661b2..b06dd24 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -43,6 +43,7 @@ class cuda_device_runtime { std::map<void*, device_launch_config_t> g_cuda_device_launch_param_map; std::list<device_launch_operation_t> g_cuda_device_launch_op; unsigned g_kernel_launch_latency; + unsigned g_TB_launch_latency; unsigned long long g_max_total_param_size; bool g_cdp_enabled; diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc index 9f7e760..3e96984 100644 --- a/src/cuda-sim/ptx-stats.cc +++ b/src/cuda-sim/ptx-stats.cc @@ -168,9 +168,10 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn) { void ptx_stats::ptx_file_line_stats_add_latency(unsigned pc, unsigned latency) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); - ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), - pInsn->source_line())] - .latency += latency; + if (pInsn != NULL) + ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), + pInsn->source_line())] + .latency += latency; } // attribute dram traffic to this ptx instruction (specified by the pc) @@ -179,9 +180,10 @@ void ptx_stats::ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); - ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), - pInsn->source_line())] - .dram_traffic += dram_traffic; + if (pInsn != NULL) + ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), + pInsn->source_line())] + .dram_traffic += dram_traffic; } // attribute the number of shared memory access cycles to a ptx instruction @@ -191,10 +193,12 @@ void ptx_stats::ptx_file_line_stats_add_smem_bank_conflict( unsigned pc, unsigned n_way_bkconflict) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); - ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( - pInsn->source_file(), pInsn->source_line())]; - line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict; - line_stats.smem_warp_count += 1; + if (pInsn != NULL) { + ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( + pInsn->source_file(), pInsn->source_line())]; + line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict; + line_stats.smem_warp_count += 1; + } } // attribute a non-coalesced mem access to a ptx instruction @@ -204,10 +208,12 @@ void ptx_stats::ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); - ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( - pInsn->source_file(), pInsn->source_line())]; - line_stats.gmem_n_access_total += n_access; - line_stats.gmem_warp_count += 1; + if (pInsn != NULL) { + ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( + pInsn->source_file(), pInsn->source_line())]; + line_stats.gmem_n_access_total += n_access; + line_stats.gmem_warp_count += 1; + } } // a class that tracks the inflight memory instructions of a shader core diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 8c4ad4d..4243941 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1339,12 +1339,12 @@ class function_info { memory_space *param_mem, gpgpu_t *gpu, dim3 gridDim, dim3 blockDim); - const struct gpgpu_ptx_sim_info *get_kernel_info() const { + virtual const struct gpgpu_ptx_sim_info *get_kernel_info() const { assert(m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } - const void set_kernel_info(const struct gpgpu_ptx_sim_info &info) { + virtual const void set_kernel_info(const struct gpgpu_ptx_sim_info &info) { m_kernel_info = info; m_kernel_info.ptx_version = 10 * get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); @@ -1380,6 +1380,11 @@ class function_info { // backward pointer class gpgpu_context *gpgpu_ctx; + protected: + // Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along + // with ___.ptx + struct gpgpu_ptx_sim_info m_kernel_info; + private: unsigned maxnt_id; unsigned m_uid; @@ -1405,7 +1410,7 @@ class function_info { // Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along // with ___.ptx - struct gpgpu_ptx_sim_info m_kernel_info; + // with ___.ptx symbol_table *m_symtab; diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 372bda4..4e91763 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -38,7 +38,8 @@ /// extern prototypes -extern int ptx_error(yyscan_t yyscanner, const char *s); +extern int ptx_error(yyscan_t yyscanner, ptx_recognizer *recognizer, + const char *s); extern int ptx_lex_init(yyscan_t *scanner); extern void ptx_set_in(FILE *_in_str, yyscan_t yyscanner); extern int ptx_parse(yyscan_t scanner, ptx_recognizer *recognizer); diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 549c08c..afdb41b 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -36,7 +36,8 @@ typedef void *yyscan_t; extern int ptx_get_lineno(yyscan_t yyscanner); extern YYSTYPE *ptx_get_lval(yyscan_t yyscanner); -extern int ptx_error(yyscan_t yyscanner, const char *s); +extern int ptx_error(yyscan_t yyscanner, ptx_recognizer *recognizer, + const char *s); extern int ptx_lex_init(yyscan_t *scanner); extern void ptx_set_in(FILE *_in_str, yyscan_t yyscanner); extern FILE *ptx_get_in(yyscan_t yyscanner); @@ -225,7 +226,7 @@ void ptx_recognizer::parse_error_impl(const char *file, unsigned line, g_error_detected = 1; printf("%s:%u: Parse error: %s (%s:%u)\n\n", gpgpu_ctx->g_filename, ptx_get_lineno(scanner), buf, file, line); - ptx_error(scanner, NULL); + ptx_error(scanner, this, NULL); abort(); exit(1); } diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 655d790..19714ec 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -27,12 +27,16 @@ // POSSIBILITY OF SUCH DAMAGE. #include "addrdec.h" +#include <math.h> #include <string.h> #include "../option_parser.h" #include "gpu-sim.h" +#include "hashing.h" static long int powli(long int x, long int y); static unsigned int LOGB2_32(unsigned int v); +static unsigned next_powerOf2(unsigned n); + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low); static void addrdec_getmasklimit(new_addr_type mask, unsigned char *high, @@ -65,7 +69,8 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) { "= new add. mask + flipped bank sel and chip sel bits", "0"); option_parser_register( - opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, + opp, "-gpgpu_memory_partition_indexing", OPT_UINT32, + &memory_partition_indexing, "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing", "0"); } @@ -89,7 +94,7 @@ new_addr_type linear_to_raw_address_translation::partition_address( void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_t *tlx) const { - unsigned long long int addr_for_chip, rest_of_addr; + unsigned long long int addr_for_chip, rest_of_addr, rest_of_addr_high_bits; if (!gap) { tlx->chip = addrdec_packbits(addrdec_mask[CHIP], addr, addrdec_mkhigh[CHIP], addrdec_mklow[CHIP]); @@ -101,6 +106,9 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_mklow[COL]); tlx->burst = addrdec_packbits(addrdec_mask[BURST], addr, addrdec_mkhigh[BURST], addrdec_mklow[BURST]); + rest_of_addr_high_bits = + (addr >> (ADDR_CHIP_S + (log2channel + log2sub_partition))); + } else { // Split the given address at ADDR_CHIP_S into (MSBs,LSBs) // - extract chip address using modulus of MSBs @@ -108,6 +116,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, // the LSBs addr_for_chip = (addr >> ADDR_CHIP_S) % m_n_channel; rest_of_addr = ((addr >> ADDR_CHIP_S) / m_n_channel) << ADDR_CHIP_S; + rest_of_addr_high_bits = ((addr >> ADDR_CHIP_S) / m_n_channel); rest_of_addr |= addr & ((1 << ADDR_CHIP_S) - 1); tlx->chip = addr_for_chip; @@ -127,68 +136,35 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, break; case BITWISE_PERMUTATION: { assert(!gap); - tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel - 1)); + tlx->chip = + bitwise_hash_function(rest_of_addr_high_bits, tlx->chip, m_n_channel); assert(tlx->chip < m_n_channel); break; } case IPOLY: { - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * - * equations are adopted from: - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - */ - if (m_n_channel == 32) { - std::bitset<64> a(tlx->row); - std::bitset<5> chip(tlx->chip); - chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ - a[0] ^ chip[0]; - chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ - a[1] ^ chip[1]; - chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ - a[0] ^ chip[2]; - chip[3] = - a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3]; - chip[4] = - a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4]; - tlx->chip = chip.to_ulong(); + // assert(!gap); + unsigned sub_partition_addr_mask = m_n_sub_partition_in_channel - 1; + unsigned sub_partition = tlx->chip * m_n_sub_partition_in_channel + + (tlx->bk & sub_partition_addr_mask); + sub_partition = ipoly_hash_function( + rest_of_addr_high_bits, sub_partition, + nextPowerOf2_m_n_channel * m_n_sub_partition_in_channel); - } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_partition_indexing error: The number of " - "channels should be " - "32 for the hashing IPOLY index function.\n" && - 0); - } - assert(tlx->chip < m_n_channel); - break; - } - case PAE: { - // Page Address Entropy - // random selected bits from the page and bank bits - // similar to - // Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address - // Mapping for GPUs." ISCA 2018 - std::bitset<64> a(tlx->row); - std::bitset<5> chip(tlx->chip); - std::bitset<4> b(tlx->bk); - chip[0] = a[13] ^ a[10] ^ a[9] ^ a[5] ^ a[0] ^ b[3] ^ b[0] ^ chip[0]; - chip[1] = a[12] ^ a[11] ^ a[6] ^ a[1] ^ b[3] ^ b[2] ^ b[1] ^ chip[1]; - chip[2] = a[14] ^ a[9] ^ a[8] ^ a[7] ^ a[2] ^ b[1] ^ chip[2]; - chip[3] = a[11] ^ a[10] ^ a[8] ^ a[3] ^ b[2] ^ b[3] ^ chip[3]; - chip[4] = a[12] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ b[1] ^ b[0] ^ chip[4]; - tlx->chip = chip.to_ulong(); + if (gap) // if it is not 2^n partitions, then take modular + sub_partition = + sub_partition % (m_n_channel * m_n_sub_partition_in_channel); + + tlx->chip = sub_partition / m_n_sub_partition_in_channel; + tlx->sub_partition = sub_partition; assert(tlx->chip < m_n_channel); + assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); + return; break; } case RANDOM: { // This is an unrealistic hashing using software hashtable // we generate a random set for each memory address and save the value in - // a big hashtable for future reuse - new_addr_type chip_address = (addr >> ADDR_CHIP_S); + new_addr_type chip_address = (addr >> (ADDR_CHIP_S - log2sub_partition)); tr1_hash_map<new_addr_type, unsigned>::const_iterator got = address_random_interleaving.find(chip_address); if (got == address_random_interleaving.end()) { @@ -308,8 +284,12 @@ void linear_to_raw_address_translation::init( unsigned i; unsigned long long int mask; unsigned int nchipbits = ::LOGB2_32(n_channel); + log2channel = nchipbits; + log2sub_partition = ::LOGB2_32(n_sub_partition_in_channel); m_n_channel = n_channel; m_n_sub_partition_in_channel = n_sub_partition_in_channel; + nextPowerOf2_m_n_channel = ::next_powerOf2(n_channel); + m_n_sub_partition_total = n_channel * n_sub_partition_in_channel; gap = (n_channel - ::powli(2, nchipbits)); if (gap) { @@ -596,6 +576,22 @@ static unsigned int LOGB2_32(unsigned int v) { return r; } +// compute power of two greater than or equal to n +// https://www.techiedelight.com/round-next-highest-power-2/ +unsigned next_powerOf2(unsigned n) { + // decrement n (to handle the case when n itself + // is a power of 2) + n = n - 1; + + // do till only one bit is left + while (n & n - 1) n = n & (n - 1); // unset rightmost bit + + // n is now a power of two (less than n) + + // return next power of 2 + return n << 1; +} + static new_addr_type addrdec_packbits(new_addr_type mask, new_addr_type val, unsigned char high, unsigned char low) { unsigned pos = 0; diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index 03b84a4..d8db416 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -87,6 +87,10 @@ class linear_to_raw_address_translation { unsigned int gap; unsigned m_n_channel; int m_n_sub_partition_in_channel; + int m_n_sub_partition_total; + unsigned log2channel; + unsigned log2sub_partition; + unsigned nextPowerOf2_m_n_channel; }; #endif diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 02356b2..ca47c46 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -31,6 +31,7 @@ #include "dram_sched.h" #include "gpu-misc.h" #include "gpu-sim.h" +#include "hashing.h" #include "l2cache.h" #include "mem_fetch.h" #include "mem_latency_stat.h" @@ -207,8 +208,18 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, } case BITWISE_XORING_BK_INDEX: { // xoring bank bits with lower bits of the page - int lbank = log2(banks); - bk = tlx.bk ^ (tlx.row & ((1 << lbank) - 1)); + bk = bitwise_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); + break; + } + case IPOLY_BK_INDEX: { + /*IPOLY for bank indexing function from "Pseudo-randomly interleaved + * memory." Rau, B. R et al. ISCA 1991 + * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf + */ + // xoring bank bits with lower bits of the page + bk = ipoly_hash_function(tlx.row, tlx.bk, banks); + assert(bk < banks); break; } case CUSTOM_BK_INDEX: diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 2e39a43..6c212e9 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -97,6 +97,7 @@ struct bank_t { enum bank_index_function { LINEAR_BK_INDEX = 0, BITWISE_XORING_BK_INDEX, + IPOLY_BK_INDEX, CUSTOM_BK_INDEX }; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index af22c4c..75c3691 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -29,6 +29,7 @@ #include "gpu-cache.h" #include <assert.h> #include "gpu-sim.h" +#include "hashing.h" #include "stat-tool.h" // used to allocate memory that is large enough to adapt the changes in cache @@ -62,24 +63,31 @@ unsigned l1d_cache_config::set_bank(new_addr_type addr) const { // For sector cache, we select one sector per bank (sector interleaving) // This is what was found in Volta (one sector per bank, sector interleaving) // otherwise, line interleaving - if (m_cache_type == SECTOR) - return (addr >> m_sector_sz_log2) & (l1_banks - 1); - else - return (addr >> m_line_sz_log2) & (l1_banks - 1); + return cache_config::hash_function(addr, l1_banks, l1_banks_byte_interleaving, + m_l1_banks_log2, + l1_banks_hashing_function); +} + +unsigned cache_config::set_index(new_addr_type addr) const { + return cache_config::hash_function(addr, m_nset, m_line_sz_log2, m_nset_log2, + m_set_index_function); } -unsigned l1d_cache_config::set_index(new_addr_type addr) const { - unsigned set_index = m_nset; // Default to linear set index function - unsigned lower_xor = 0; - unsigned upper_xor = 0; +unsigned cache_config::hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, + unsigned m_nset_log2, + unsigned m_index_function) const { + unsigned set_index = 0; - switch (m_set_index_function) { - case FERMI_HASH_SET_FUNCTION: - case BITWISE_XORING_FUNCTION: + switch (m_index_function) { + case FERMI_HASH_SET_FUNCTION: { /* * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse * Distance Theory" Cedric Nugteren et al. HPCA 2014 */ + unsigned lower_xor = 0; + unsigned upper_xor = 0; + if (m_nset == 32 || m_nset == 64) { // Lower xor value is bits 7-11 lower_xor = (addr >> m_line_sz_log2) & 0x1F; @@ -102,54 +110,34 @@ unsigned l1d_cache_config::set_index(new_addr_type addr) const { 0); } break; + } - case HASH_IPOLY_FUNCTION: - /* - * Set Indexing function from "Pseudo-randomly interleaved memory." - * Rau, B. R et al. - * ISCA 1991 - * - * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu - * cache management scheme." Khairy et al. IEEE TPDS 2017. - */ - if (m_nset == 32 || m_nset == 64) { - std::bitset<64> a(addr); - std::bitset<6> index; - index[0] = a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[18] ^ a[17] ^ - a[15] ^ a[12] ^ a[7]; // 10 - index[1] = a[26] ^ a[25] ^ a[24] ^ a[23] ^ a[22] ^ a[19] ^ a[18] ^ - a[16] ^ a[13] ^ a[8]; // 10 - index[2] = a[26] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[18] ^ a[15] ^ - a[14] ^ a[12] ^ a[9]; // 10 - index[3] = a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[19] ^ a[16] ^ a[15] ^ - a[13] ^ a[10]; // 9 - index[4] = a[24] ^ a[23] ^ a[22] ^ a[21] ^ a[20] ^ a[17] ^ a[16] ^ - a[14] ^ a[11]; // 9 - - if (m_nset == 64) index[5] = a[12]; - - set_index = index.to_ulong(); - - } else { /* Else incorrect number of sets for the hashing function */ - assert( - "\nGPGPU-Sim cache configuration error: The number of sets should " - "be " - "32 or 64 for the hashing set index function.\n" && - 0); - } + case BITWISE_XORING_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = bitwise_hash_function(higher_bits, index, m_nset); break; - - case CUSTOM_SET_FUNCTION: + } + case HASH_IPOLY_FUNCTION: { + new_addr_type higher_bits = addr >> (m_line_sz_log2 + m_nset_log2); + unsigned index = (addr >> m_line_sz_log2) & (m_nset - 1); + set_index = ipoly_hash_function(higher_bits, index, m_nset); + break; + } + case CUSTOM_SET_FUNCTION: { /* No custom set function implemented */ break; + } - case LINEAR_SET_FUNCTION: + case LINEAR_SET_FUNCTION: { set_index = (addr >> m_line_sz_log2) & (m_nset - 1); break; + } - default: + default: { assert("\nUndefined set index function.\n" && 0); break; + } } // Linear function selected or custom set index function not implemented @@ -166,13 +154,14 @@ void l2_cache_config::init(linear_to_raw_address_translation *address_mapping) { } unsigned l2_cache_config::set_index(new_addr_type addr) const { - if (!m_address_mapping) { - return (addr >> m_line_sz_log2) & (m_nset - 1); - } else { + new_addr_type part_addr = addr; + + if (m_address_mapping) { // Calculate set index without memory partition bits to reduce set camping - new_addr_type part_addr = m_address_mapping->partition_address(addr); - return (part_addr >> m_line_sz_log2) & (m_nset - 1); + part_addr = m_address_mapping->partition_address(addr); } + + return cache_config::set_index(part_addr); } tag_array::~tag_array() { @@ -1315,6 +1304,10 @@ enum cache_request_status data_cache::wr_miss_wa_naive( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + // the evicted block may have wrong chip id when advanced L2 hashing is + // used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1358,6 +1351,10 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + // the evicted block may have wrong chip id when advanced L2 hashing is + // used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1424,6 +1421,10 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + // the evicted block may have wrong chip id when advanced L2 hashing is + // used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1473,6 +1474,10 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + // the evicted block may have wrong chip id when advanced L2 hashing is + // used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1545,6 +1550,10 @@ enum cache_request_status data_cache::rd_miss_base( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + // the evicted block may have wrong chip id when advanced L2 hashing is + // used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events); } return MISS; diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 2a37876..5c28b41 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -686,17 +686,11 @@ class cache_config { m_line_sz * m_nset * m_assoc, m_nset, m_assoc, m_line_sz); } - virtual unsigned set_index(new_addr_type addr) const { - if (m_set_index_function != LINEAR_SET_FUNCTION) { - printf( - "\nGPGPU-Sim cache configuration error: Hashing or " - "custom set index function selected in configuration " - "file for a cache that has not overloaded the set_index " - "function\n"); - abort(); - } - return (addr >> m_line_sz_log2) & (m_nset - 1); - } + virtual unsigned set_index(new_addr_type addr) const; + + unsigned hash_function(new_addr_type addr, unsigned m_nset, + unsigned m_line_sz_log2, unsigned m_nset_log2, + unsigned m_index_function) const; new_addr_type tag(new_addr_type addr) const { // For generality, the tag includes both index and tag. This allows for more @@ -793,10 +787,18 @@ class cache_config { class l1d_cache_config : public cache_config { public: l1d_cache_config() : cache_config() {} - virtual unsigned set_index(new_addr_type addr) const; unsigned set_bank(new_addr_type addr) const; + void init(char *config, FuncCache status) { + m_banks_byte_interleaving_log2 = LOGB2(l1_banks_byte_interleaving); + m_l1_banks_log2 = LOGB2(l1_banks); + cache_config::init(config, status); + } unsigned l1_latency; unsigned l1_banks; + unsigned m_l1_banks_log2; + unsigned l1_banks_byte_interleaving; + unsigned m_banks_byte_interleaving_log2; + unsigned l1_banks_hashing_function; }; class l2_cache_config : public cache_config { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index a6a39ab..1650688 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -129,9 +129,10 @@ void power_config::reg_options(class OptionParser *opp) { } void memory_config::reg_options(class OptionParser *opp) { - option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, - "Fill the L2 cache on memcpy", "1"); - option_parser_register(opp, "-simple_dram_model", OPT_BOOL, + option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, + &m_perf_sim_memcpy, "Fill the L2 cache on memcpy", + "1"); + option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, &simple_dram_model, "simple_dram_model with fixed latency and BW", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, @@ -187,11 +188,11 @@ void memory_config::reg_options(class OptionParser *opp) { "DRAM timing parameters = " "{nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); - option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency, + option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency, "ROP queue latency (default 85)", "85"); option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); - option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, + option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, &dual_bus_interface, "dual_bus_interface (default = 0) ", "0"); option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, @@ -204,13 +205,13 @@ void memory_config::reg_options(class OptionParser *opp) { "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 " "= take lower bits) (Default = 0)", "0"); - option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, + option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, &seperate_write_queue_enabled, "Seperate_Write_Queue_Enable", "0"); - option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, + option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); option_parser_register( - opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", "0"); option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, "icnt_flit_size", "32"); @@ -248,11 +249,18 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, - "The number of L1 cache banks", "1"); - option_parser_register(opp, "-l1_latency", OPT_UINT32, + option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, + &m_L1D_config.l1_banks, "The number of L1 cache banks", + "1"); + option_parser_register(opp, "-gpgpu_l1_banks_byte_interleaving", OPT_UINT32, + &m_L1D_config.l1_banks_byte_interleaving, + "l1 banks byte interleaving granularity", "32"); + option_parser_register(opp, "-gpgpu_l1_banks_hashing_function", OPT_UINT32, + &m_L1D_config.l1_banks_hashing_function, + "l1 banks hashing function", "0"); + option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); - option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency, + option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, "smem Latency", "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, @@ -266,7 +274,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, + option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, "global memory access skip L1D cache (implements " "-Xptxas -dlcm=cg, default=no skip)", "0"); @@ -318,7 +326,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adaptive_cache_config", OPT_BOOL, + option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, &adaptive_cache_config, "adaptive_cache_config", "0"); option_parser_register( opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault, @@ -343,7 +351,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { "memory bank conflict check ", "2"); option_parser_register( - opp, "-mem_unit_ports", OPT_INT32, &mem_unit_ports, + opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports, "The number of memory transactions allowed per core cycle", "1"); option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, @@ -369,10 +377,11 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id, "Use warp ID in mapping registers to banks (default = off)", "0"); - option_parser_register(opp, "-sub_core_model", OPT_BOOL, &sub_core_model, + option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, + &sub_core_model, "Sub Core Volta/Pascal model (default = off)", "0"); - option_parser_register(opp, "-enable_specialized_operand_collector", OPT_BOOL, - &enable_specialized_operand_collector, + option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", + OPT_BOOL, &enable_specialized_operand_collector, "enable_specialized_operand_collector", "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp, @@ -496,7 +505,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { "1"); option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, - "Number of tensor_core units (default=1)", "1"); + "Number of tensor_core units (default=1)", "0"); option_parser_register( opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", @@ -515,6 +524,28 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, "Support concurrent kernels on a SM (default = disabled)", "0"); + option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, + &perfect_inst_const_cache, + "perfect inst and const cache mode, so all inst and " + "const hits in the cache(default = disabled)", + "0"); + option_parser_register( + opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + "the number of fetched intruction per warp each cycle", "1"); + option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, + ®_file_port_throughput, + "the number ports of the register file", "1"); + + for (unsigned j = 0; j < SPECIALIZED_UNIT_NUM; ++j) { + std::stringstream ss; + ss << "-specialized_unit_" << j + 1; + option_parser_register(opp, ss.str().c_str(), OPT_CSTR, + &specialized_unit_string[j], + "specialized unit config" + " {<enabled>,<num_units>:<latency>:<initiation>,<ID_" + "OC_SPEC>:<OC_EX_SPEC>,<NAME>}", + "0,4,4,4,4,BRA"); + } } void gpgpu_sim_config::reg_options(option_parser_t opp) { @@ -620,6 +651,11 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) { option_parser_register(opp, "-gpgpu_cdp_enabled", OPT_BOOL, &(gpgpu_ctx->device_runtime->g_cdp_enabled), "Turn on CDP", "0"); + + option_parser_register(opp, "-gpgpu_TB_launch_latency", OPT_INT32, + &(gpgpu_ctx->device_runtime->g_TB_launch_latency), + "thread block launch latency in cycles. Default: 0", + "0"); } ///////////////////////////////////////////////////////////////////////////// @@ -696,9 +732,17 @@ bool gpgpu_sim::get_more_cta_left() const { return false; } +void gpgpu_sim::decrement_kernel_latency() { + for (unsigned n = 0; n < m_running_kernels.size(); n++) { + if (m_running_kernels[n] && m_running_kernels[n]->m_kernel_TB_latency) + m_running_kernels[n]->m_kernel_TB_latency--; + } +} + kernel_info_t *gpgpu_sim::select_kernel() { if (m_running_kernels[m_last_issued_kernel] && - !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run()) { + !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run() && + !m_running_kernels[m_last_issued_kernel]->m_kernel_TB_latency) { unsigned launch_uid = m_running_kernels[m_last_issued_kernel]->get_uid(); if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { @@ -714,7 +758,8 @@ kernel_info_t *gpgpu_sim::select_kernel() { for (unsigned n = 0; n < m_running_kernels.size(); n++) { unsigned idx = (n + m_last_issued_kernel + 1) % m_config.max_concurrent_kernel; - if (kernel_more_cta_left(m_running_kernels[idx])) { + if (kernel_more_cta_left(m_running_kernels[idx]) && + !m_running_kernels[idx]->m_kernel_TB_latency) { m_last_issued_kernel = idx; m_running_kernels[idx]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; // record this kernel for stat print if it is the first time this kernel @@ -763,6 +808,14 @@ void gpgpu_sim::stop_all_running_kernels() { } } +void exec_gpgpu_sim::createSIMTCluster() { + m_cluster = new simt_core_cluster *[m_shader_config->n_simt_clusters]; + for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++) + m_cluster[i] = + new exec_simt_core_cluster(this, i, m_shader_config, m_memory_config, + m_shader_stats, m_memory_stats); +} + gpgpu_sim::gpgpu_sim(const gpgpu_sim_config &config, gpgpu_context *ctx) : gpgpu_t(config, ctx), m_config(config) { gpgpu_ctx = ctx; @@ -803,12 +856,6 @@ gpgpu_sim::gpgpu_sim(const gpgpu_sim_config &config, gpgpu_context *ctx) partiton_replys_in_parallel = 0; partiton_replys_in_parallel_total = 0; - m_cluster = new simt_core_cluster *[m_shader_config->n_simt_clusters]; - for (unsigned i = 0; i < m_shader_config->n_simt_clusters; i++) - m_cluster[i] = - new simt_core_cluster(this, i, m_shader_config, m_memory_config, - m_shader_stats, m_memory_stats); - m_memory_partition_unit = new memory_partition_unit *[m_memory_config->m_n_mem]; m_memory_sub_partition = @@ -1518,6 +1565,14 @@ void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, * object that tells us which kernel to ask for a CTA from */ +unsigned exec_shader_core_ctx::sim_init_thread( + kernel_info_t &kernel, ptx_thread_info **thread_info, int sid, unsigned tid, + unsigned threads_left, unsigned num_threads, core_t *core, + unsigned hw_cta_id, unsigned hw_warp_id, gpgpu_t *gpu) { + return ptx_sim_init_thread(kernel, thread_info, sid, tid, threads_left, + num_threads, core, hw_cta_id, hw_warp_id, gpu); +} + void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { if (!m_config->gpgpu_concurrent_kernel_sm) set_max_cta(kernel); @@ -1583,7 +1638,7 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { for (unsigned i = start_thread; i < end_thread; i++) { m_threadState[i].m_cta_id = free_cta_hw_id; unsigned warp_id = i / m_config->warp_size; - nthreads_in_block += ptx_sim_init_thread( + nthreads_in_block += sim_init_thread( kernel, &m_thread[i], m_sid, i, cta_size - (i - start_thread), m_config->n_thread_per_shader, this, free_cta_hw_id, warp_id, m_cluster->get_gpu()); @@ -1621,8 +1676,7 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { m_barriers.allocate_barrier(free_cta_hw_id, warps); // initialize the SIMT stacks and fetch hardware - init_warps(free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, - kernel.get_uid()); + init_warps(free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, kernel); m_n_active_cta++; shader_CTA_count_log(m_sid, 1); @@ -1814,6 +1868,7 @@ void gpgpu_sim::cycle() { #endif issue_block2core(); + decrement_kernel_latency(); // Depending on configuration, invalidate the caches once all of threads are // completed. @@ -1921,12 +1976,15 @@ void shader_core_ctx::dump_warp_state(FILE *fout) const { fprintf(fout, "\n"); fprintf(fout, "per warp functional simulation status:\n"); for (unsigned w = 0; w < m_config->max_warps_per_shader; w++) - m_warp[w].print(fout); + m_warp[w]->print(fout); } void gpgpu_sim::perf_memcpy_to_gpu(size_t dst_start_addr, size_t count) { if (m_memory_config->m_perf_sim_memcpy) { - assert(dst_start_addr % 32 == 0); + // if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime + // can start nre data structure at any position assert (dst_start_addr % + // 32 + //== 0); for (unsigned counter = 0; counter < count; counter += 32) { const unsigned wr_addr = dst_start_addr + counter; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 19fbf5d..2e6820d 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -370,6 +370,8 @@ class gpgpu_sim_config : public power_config, return runtime_pending_launch_count_limit; } + bool flush_l1() const { return gpgpu_flush_l1_cache; } + private: void init_clock_domains(void); @@ -525,6 +527,7 @@ class gpgpu_sim : public gpgpu_t { bool kernel_more_cta_left(kernel_info_t *kernel) const; bool hit_max_cta_count() const; kernel_info_t *select_kernel(); + void decrement_kernel_latency(); const gpgpu_sim_config &get_config() const { return m_config; } void gpu_print_stat(); @@ -577,8 +580,8 @@ class gpgpu_sim : public gpgpu_t { void gpgpu_debug(); + protected: ///// data ///// - class simt_core_cluster **m_cluster; class memory_partition_unit **m_memory_partition_unit; class memory_sub_partition **m_memory_sub_partition; @@ -633,6 +636,7 @@ class gpgpu_sim : public gpgpu_t { // into a string for stat printout void clear_executed_kernel_info(); //< clear the kernel information after // stat printout + virtual void createSIMTCluster() = 0; public: unsigned long long gpu_sim_insn; @@ -681,4 +685,14 @@ class gpgpu_sim : public gpgpu_t { } }; +class exec_gpgpu_sim : public gpgpu_sim { + public: + exec_gpgpu_sim(const gpgpu_sim_config &config, gpgpu_context *ctx) + : gpgpu_sim(config, ctx) { + createSIMTCluster(); + } + + virtual void createSIMTCluster(); +}; + #endif diff --git a/src/gpgpu-sim/hashing.cc b/src/gpgpu-sim/hashing.cc new file mode 100644 index 0000000..f566aa4 --- /dev/null +++ b/src/gpgpu-sim/hashing.cc @@ -0,0 +1,125 @@ +// author: Mahmoud Khairy, (Purdue Univ) +// email: [email protected] + +#include <math.h> +#include <string.h> +#include "../abstract_hardware_model.h" +#include "gpu-cache.h" + +unsigned ipoly_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num) { + /* + * Set Indexing function from "Pseudo-randomly interleaved memory." + * Rau, B. R et al. + * ISCA 1991 + * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf + * + * equations are corresponding to IPOLY(37) and are adopted from: + * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu + * cache management scheme." Khairy et al. IEEE TPDS 2017. + * + * equations for 16 banks are corresponding to IPOLY(5) + * equations for 32 banks are corresponding to IPOLY(37) + * equations for 64 banks are corresponding to IPOLY(67) + * To see all the IPOLY equations for all the degrees, see + * http://wireless-systems.ece.gatech.edu/6604/handouts/Peterson's%20Table.pdf + * + * We generate these equations using GF(2) arithmetic: + * http://www.ee.unb.ca/cgi-bin/tervo/calc.pl?num=&den=&f=d&e=1&m=1 + * + * We go through all the strides 128 (10000000), 256 (100000000),... and + * do modular arithmetic in GF(2) Then, we create the H-matrix and group + * each bit together, for more info read the ISCA 1991 paper + * + * IPOLY hashing guarantees conflict-free for all 2^n strides which widely + * exit in GPGPU applications and also show good performance for other + * strides. + */ + if (bank_set_num == 16) { + std::bitset<64> a(higher_bits); + std::bitset<4> b(index); + std::bitset<4> new_index(index); + + new_index[0] = + a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[6] ^ a[4] ^ a[3] ^ a[0] ^ b[0]; + new_index[1] = + a[12] ^ a[8] ^ a[7] ^ a[6] ^ a[5] ^ a[3] ^ a[1] ^ a[0] ^ b[1]; + new_index[2] = a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[4] ^ a[2] ^ a[1] ^ b[2]; + new_index[3] = a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[5] ^ a[3] ^ a[2] ^ b[3]; + + return new_index.to_ulong(); + + } else if (bank_set_num == 32) { + std::bitset<64> a(higher_bits); + std::bitset<5> b(index); + std::bitset<5> new_index(index); + + new_index[0] = + a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ a[0] ^ b[0]; + new_index[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ + a[1] ^ b[1]; + new_index[2] = + a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ a[0] ^ b[2]; + new_index[3] = + a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ b[3]; + new_index[4] = + a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ b[4]; + return new_index.to_ulong(); + + } else if (bank_set_num == 64) { + std::bitset<64> a(higher_bits); + std::bitset<6> b(index); + std::bitset<6> new_index(index); + + new_index[0] = a[18] ^ a[17] ^ a[16] ^ a[15] ^ a[12] ^ a[10] ^ a[6] ^ a[5] ^ + a[0] ^ b[0]; + new_index[1] = a[15] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[5] ^ a[1] ^ + a[0] ^ b[1]; + new_index[2] = a[16] ^ a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[8] ^ a[6] ^ a[2] ^ + a[1] ^ b[2]; + new_index[3] = a[17] ^ a[15] ^ a[14] ^ a[13] ^ a[12] ^ a[9] ^ a[7] ^ a[3] ^ + a[2] ^ b[3]; + new_index[4] = a[18] ^ a[16] ^ a[15] ^ a[14] ^ a[13] ^ a[10] ^ a[8] ^ a[4] ^ + a[3] ^ b[4]; + new_index[5] = + a[17] ^ a[16] ^ a[15] ^ a[14] ^ a[11] ^ a[9] ^ a[5] ^ a[4] ^ b[5]; + return new_index.to_ulong(); + } else { /* Else incorrect number of channels for the hashing function */ + assert( + "\nmemory_partition_indexing error: The number of " + "channels should be " + "16, 32 or 64 for the hashing IPOLY index function. other banks " + "numbers are not supported. Generate it by yourself! \n" && + 0); + + return 0; + } +} + +unsigned bitwise_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num) { + return (index) ^ (higher_bits & (bank_set_num - 1)); +} + +unsigned PAE_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num) { + // Page Address Entropy + // random selected bits from the page and bank bits + // similar to + // Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address + if (bank_set_num == 32) { + std::bitset<64> a(higher_bits); + std::bitset<5> b(index); + std::bitset<5> new_index(index); + new_index[0] = a[13] ^ a[10] ^ a[9] ^ a[5] ^ a[0] ^ b[3] ^ b[0] ^ b[0]; + new_index[1] = a[12] ^ a[11] ^ a[6] ^ a[1] ^ b[3] ^ b[2] ^ b[1] ^ b[1]; + new_index[2] = a[14] ^ a[9] ^ a[8] ^ a[7] ^ a[2] ^ b[1] ^ b[2]; + new_index[3] = a[11] ^ a[10] ^ a[8] ^ a[3] ^ b[2] ^ b[3] ^ b[3]; + new_index[4] = a[12] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ b[1] ^ b[0] ^ b[4]; + + return new_index.to_ulong(); + } else { + assert(0); + return 0; + } +} diff --git a/src/gpgpu-sim/hashing.h b/src/gpgpu-sim/hashing.h new file mode 100644 index 0000000..867c949 --- /dev/null +++ b/src/gpgpu-sim/hashing.h @@ -0,0 +1,24 @@ +// author: Mahmoud Khairy, (Purdue Univ) +// email: [email protected] + +#include <assert.h> +#include <stdio.h> +#include <stdlib.h> +#include "../option_parser.h" + +#ifndef HASHING_H +#define HASHING_H + +#include "../abstract_hardware_model.h" +#include "gpu-cache.h" + +unsigned ipoly_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num); + +unsigned bitwise_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num); + +unsigned PAE_hash_function(new_addr_type higher_bits, unsigned index, + unsigned bank_set_num); + +#endif diff --git a/src/gpgpu-sim/icnt_wrapper.cc b/src/gpgpu-sim/icnt_wrapper.cc index 890638a..82785dc 100644 --- a/src/gpgpu-sim/icnt_wrapper.cc +++ b/src/gpgpu-sim/icnt_wrapper.cc @@ -144,16 +144,20 @@ void icnt_reg_options(class OptionParser* opp) { "Interconnection network config file", "mesh"); // parameters for local xbar - option_parser_register(opp, "-inct_in_buffer_limit", OPT_UINT32, + option_parser_register(opp, "-icnt_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64"); - option_parser_register(opp, "-inct_out_buffer_limit", OPT_UINT32, + option_parser_register(opp, "-icnt_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64"); - option_parser_register(opp, "-inct_subnets", OPT_UINT32, + option_parser_register(opp, "-icnt_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2"); - option_parser_register(opp, "-arbiter_algo", OPT_UINT32, + option_parser_register(opp, "-icnt_arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1"); + option_parser_register(opp, "-icnt_verbose", OPT_UINT32, + &g_inct_config.verbose, "inct_verbose", "0"); + option_parser_register(opp, "-icnt_grant_cycles", OPT_UINT32, + &g_inct_config.grant_cycles, "grant_cycles", "1"); } void icnt_wrapper_init() { diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc index cd32386..0e20462 100644 --- a/src/gpgpu-sim/local_interconnect.cc +++ b/src/gpgpu-sim/local_interconnect.cc @@ -39,20 +39,21 @@ xbar_router::xbar_router(unsigned router_id, enum Interconnect_type m_type, unsigned n_shader, unsigned n_mem, - unsigned m_in_buffer_limit, - unsigned m_out_buffer_limit, - enum Arbiteration_type m_arbit_type) { + const struct inct_config& m_localinct_config) { m_id = router_id; router_type = m_type; _n_mem = n_mem; _n_shader = n_shader; total_nodes = n_shader + n_mem; + verbose = m_localinct_config.verbose; + grant_cycles = m_localinct_config.grant_cycles; + grant_cycles_count = m_localinct_config.grant_cycles; in_buffers.resize(total_nodes); out_buffers.resize(total_nodes); next_node.resize(total_nodes, 0); - in_buffer_limit = m_in_buffer_limit; - out_buffer_limit = m_out_buffer_limit; - arbit_type = m_arbit_type; + in_buffer_limit = m_localinct_config.in_buffer_limit; + out_buffer_limit = m_localinct_config.out_buffer_limit; + arbit_type = m_localinct_config.arbiter_algo; next_node_id = 0; if (m_type == REQ_NET) { active_in_buffers = n_shader; @@ -69,6 +70,9 @@ xbar_router::xbar_router(unsigned router_id, enum Interconnect_type m_type, out_buffer_util = 0; in_buffer_util = 0; packets_num = 0; + conflicts_util = 0; + cycles_util = 0; + reqs_util = 0; } xbar_router::~xbar_router() {} @@ -117,14 +121,16 @@ void xbar_router::Advance() { } void xbar_router::RR_Advance() { - cycles++; - + bool active = false; vector<bool> issued(total_nodes, false); + unsigned conflict_sub = 0; + unsigned reqs = 0; for (unsigned i = 0; i < total_nodes; ++i) { unsigned node_id = (i + next_node_id) % total_nodes; if (!in_buffers[node_id].empty()) { + active = true; Packet _packet = in_buffers[node_id].front(); // ensure that the outbuffer has space and not issued before in this cycle if (Has_Buffer_Out(_packet.output_deviceID, 1)) { @@ -132,23 +138,38 @@ void xbar_router::RR_Advance() { out_buffers[_packet.output_deviceID].push(_packet); in_buffers[node_id].pop(); issued[_packet.output_deviceID] = true; + reqs++; } else - conflicts++; + conflict_sub++; } else { out_buffer_full++; - if (issued[_packet.output_deviceID]) conflicts++; + if (issued[_packet.output_deviceID]) conflict_sub++; } } } next_node_id = (++next_node_id % total_nodes); + conflicts += conflict_sub; + if (active) { + conflicts_util += conflict_sub; + cycles_util++; + reqs_util += reqs; + } + + if (verbose) { + printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub); + printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs); + } + // collect some stats about buffer util for (unsigned i = 0; i < total_nodes; ++i) { in_buffer_util += in_buffers[i].size(); out_buffer_util += out_buffers[i].size(); } + + cycles++; } // iSLIP algorithm @@ -156,9 +177,11 @@ void xbar_router::RR_Advance() { // IEEE/ACM transactions on networking 2 (1999): 188-201. // https://www.cs.rutgers.edu/~sn624/552-F18/papers/islip.pdf void xbar_router::iSLIP_Advance() { - cycles++; - vector<unsigned> node_tmp; + bool active = false; + + unsigned conflict_sub = 0; + unsigned reqs = 0; // calcaulte how many conflicts are there for stats for (unsigned i = 0; i < total_nodes; ++i) { @@ -167,15 +190,21 @@ void xbar_router::iSLIP_Advance() { if (!node_tmp.empty()) { if (std::find(node_tmp.begin(), node_tmp.end(), _packet_tmp.output_deviceID) != node_tmp.end()) { - conflicts++; + conflict_sub++; } else node_tmp.push_back(_packet_tmp.output_deviceID); } else { node_tmp.push_back(_packet_tmp.output_deviceID); } + active = true; } } + conflicts += conflict_sub; + if (active) { + conflicts_util += conflict_sub; + cycles_util++; + } // do iSLIP for (unsigned i = 0; i < total_nodes; ++i) { if (Has_Buffer_Out(i, 1)) { @@ -187,7 +216,25 @@ void xbar_router::iSLIP_Advance() { if (_packet.output_deviceID == i) { out_buffers[_packet.output_deviceID].push(_packet); in_buffers[node_id].pop(); - next_node[i] = (++node_id % total_nodes); + if (verbose) + printf("%d : cycle %d : send req from %d to %d\n", m_id, cycles, + node_id, i - _n_shader); + if (grant_cycles_count == 1) + next_node[i] = (++node_id % total_nodes); + if (verbose) { + for (unsigned k = j + 1; k < total_nodes; ++k) { + unsigned node_id2 = (k + next_node[i]) % total_nodes; + if (!in_buffers[node_id2].empty()) { + Packet _packet2 = in_buffers[node_id2].front(); + + if (_packet2.output_deviceID == i) + printf("%d : cycle %d : cannot send req from %d to %d\n", + m_id, cycles, node_id2, i - _n_shader); + } + } + } + + reqs++; break; } } @@ -196,11 +243,30 @@ void xbar_router::iSLIP_Advance() { out_buffer_full++; } + if (active) { + reqs_util += reqs; + } + + if (verbose) + printf("%d : cycle %d : grant_cycles = %d\n", m_id, cycles, grant_cycles); + + if (active && grant_cycles_count == 1) + grant_cycles_count = grant_cycles; + else if (active) + grant_cycles_count--; + + if (verbose) { + printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub); + printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs); + } + // collect some stats about buffer util for (unsigned i = 0; i < total_nodes; ++i) { in_buffer_util += in_buffers[i].size(); out_buffer_util += out_buffers[i].size(); } + + cycles++; } bool xbar_router::Busy() const { @@ -247,9 +313,7 @@ void LocalInterconnect::CreateInterconnect(unsigned m_n_shader, net.resize(n_subnets); for (unsigned i = 0; i < n_subnets; ++i) { net[i] = new xbar_router(i, static_cast<Interconnect_type>(i), m_n_shader, - m_n_mem, m_inct_config.in_buffer_limit, - m_inct_config.out_buffer_limit, - m_inct_config.arbiter_algo); + m_n_mem, m_inct_config); } } @@ -312,51 +376,51 @@ bool LocalInterconnect::HasBuffer(unsigned deviceID, unsigned int size) const { } void LocalInterconnect::DisplayStats() const { - cout << "Req_Network_injected_packets_num = " << net[REQ_NET]->packets_num - << endl; - cout << "Req_Network_cycles = " << net[REQ_NET]->cycles << endl; - cout << "Req_Network_injected_packets_per_cycle = " - << (float)(net[REQ_NET]->packets_num) / (net[REQ_NET]->cycles) << endl; - cout << "Req_Network_conflicts_per_cycle = " - << (float)(net[REQ_NET]->conflicts) / (net[REQ_NET]->cycles) << endl; - cout << "Req_Network_in_buffer_full_per_cycle = " - << (float)(net[REQ_NET]->in_buffer_full) / (net[REQ_NET]->cycles) - << endl; - cout << "Req_Network_in_buffer_avg_util = " - << ((float)(net[REQ_NET]->in_buffer_util) / (net[REQ_NET]->cycles) / - net[REQ_NET]->active_in_buffers) - << endl; - cout << "Req_Network_out_buffer_full_per_cycle = " - << (float)(net[REQ_NET]->out_buffer_full) / (net[REQ_NET]->cycles) - << endl; - cout << "Req_Network_out_buffer_avg_util = " - << ((float)(net[REQ_NET]->out_buffer_util) / (net[REQ_NET]->cycles) / - net[REQ_NET]->active_out_buffers) - << endl; + printf("Req_Network_injected_packets_num = %lld\n", + net[REQ_NET]->packets_num); + printf("Req_Network_cycles = %lld\n", net[REQ_NET]->cycles); + printf("Req_Network_injected_packets_per_cycle = %12.4f \n", + (float)(net[REQ_NET]->packets_num) / (net[REQ_NET]->cycles)); + printf("Req_Network_conflicts_per_cycle = %12.4f\n", + (float)(net[REQ_NET]->conflicts) / (net[REQ_NET]->cycles)); + printf("Req_Network_conflicts_per_cycle_util = %12.4f\n", + (float)(net[REQ_NET]->conflicts_util) / (net[REQ_NET]->cycles_util)); + printf("Req_Bank_Level_Parallism = %12.4f\n", + (float)(net[REQ_NET]->reqs_util) / (net[REQ_NET]->cycles_util)); + printf("Req_Network_in_buffer_full_per_cycle = %12.4f\n", + (float)(net[REQ_NET]->in_buffer_full) / (net[REQ_NET]->cycles)); + printf("Req_Network_in_buffer_avg_util = %12.4f\n", + ((float)(net[REQ_NET]->in_buffer_util) / (net[REQ_NET]->cycles) / + net[REQ_NET]->active_in_buffers)); + printf("Req_Network_out_buffer_full_per_cycle = %12.4f\n", + (float)(net[REQ_NET]->out_buffer_full) / (net[REQ_NET]->cycles)); + printf("Req_Network_out_buffer_avg_util = %12.4f\n", + ((float)(net[REQ_NET]->out_buffer_util) / (net[REQ_NET]->cycles) / + net[REQ_NET]->active_out_buffers)); - cout << endl; - cout << "Reply_Network_injected_packets_num = " << net[REPLY_NET]->packets_num - << endl; - cout << "Reply_Network_cycles = " << net[REPLY_NET]->cycles << endl; - cout << "Reply_Network_injected_packets_per_cycle = " - << (float)(net[REPLY_NET]->packets_num) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_conflicts_per_cycle = " - << (float)(net[REPLY_NET]->conflicts) / (net[REPLY_NET]->cycles) << endl; - cout << "Reply_Network_in_buffer_full_per_cycle = " - << (float)(net[REPLY_NET]->in_buffer_full) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_in_buffer_avg_util = " - << ((float)(net[REPLY_NET]->in_buffer_util) / (net[REPLY_NET]->cycles) / - net[REPLY_NET]->active_in_buffers) - << endl; - cout << "Reply_Network_out_buffer_full_per_cycle = " - << (float)(net[REPLY_NET]->out_buffer_full) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_out_buffer_avg_util= " - << ((float)(net[REPLY_NET]->out_buffer_util) / (net[REPLY_NET]->cycles) / - net[REPLY_NET]->active_out_buffers) - << endl; + printf("\n"); + printf("Reply_Network_injected_packets_num = %lld\n", + net[REPLY_NET]->packets_num); + printf("Reply_Network_cycles = %lld\n", net[REPLY_NET]->cycles); + printf("Reply_Network_injected_packets_per_cycle = %12.4f\n", + (float)(net[REPLY_NET]->packets_num) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_conflicts_per_cycle = %12.4f\n", + (float)(net[REPLY_NET]->conflicts) / (net[REPLY_NET]->cycles)); + printf( + "Reply_Network_conflicts_per_cycle_util = %12.4f\n", + (float)(net[REPLY_NET]->conflicts_util) / (net[REPLY_NET]->cycles_util)); + printf("Reply_Bank_Level_Parallism = %12.4f\n", + (float)(net[REPLY_NET]->reqs_util) / (net[REPLY_NET]->cycles_util)); + printf("Reply_Network_in_buffer_full_per_cycle = %12.4f\n", + (float)(net[REPLY_NET]->in_buffer_full) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_in_buffer_avg_util = %12.4f\n", + ((float)(net[REPLY_NET]->in_buffer_util) / (net[REPLY_NET]->cycles) / + net[REPLY_NET]->active_in_buffers)); + printf("Reply_Network_out_buffer_full_per_cycle = %12.4f\n", + (float)(net[REPLY_NET]->out_buffer_full) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_out_buffer_avg_util = %12.4f\n", + ((float)(net[REPLY_NET]->out_buffer_util) / (net[REPLY_NET]->cycles) / + net[REPLY_NET]->active_out_buffers)); } void LocalInterconnect::DisplayOverallStats() const {} diff --git a/src/gpgpu-sim/local_interconnect.h b/src/gpgpu-sim/local_interconnect.h index 29cd903..dd10a06 100644 --- a/src/gpgpu-sim/local_interconnect.h +++ b/src/gpgpu-sim/local_interconnect.h @@ -45,13 +45,15 @@ struct inct_config { unsigned out_buffer_limit; unsigned subnets; Arbiteration_type arbiter_algo; + unsigned verbose; + unsigned grant_cycles; }; class xbar_router { public: xbar_router(unsigned router_id, enum Interconnect_type m_type, - unsigned n_shader, unsigned n_mem, unsigned m_in_buffer_limit, - unsigned m_out_buffer_limit, enum Arbiteration_type m_arbit_type); + unsigned n_shader, unsigned n_mem, + const struct inct_config& m_localinct_config); ~xbar_router(); void Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size); @@ -66,6 +68,9 @@ class xbar_router { // some stats unsigned long long cycles; unsigned long long conflicts; + unsigned long long conflicts_util; + unsigned long long cycles_util; + unsigned long long reqs_util; unsigned long long out_buffer_full; unsigned long long out_buffer_util; unsigned long long in_buffer_full; @@ -94,6 +99,10 @@ class xbar_router { enum Interconnect_type router_type; unsigned active_in_buffers, active_out_buffers; Arbiteration_type arbit_type; + unsigned verbose; + + unsigned grant_cycles; + unsigned grant_cycles_count; friend class LocalInterconnect; }; diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 7cb02cf..456d891 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -65,6 +65,10 @@ mem_fetch::mem_fetch(const mem_access_t &access, const warp_inst_t *inst, icnt_flit_size = config->icnt_flit_size; original_mf = m_original_mf; original_wr_mf = m_original_wr_mf; + if (m_original_mf) { + m_raw_addr.chip = m_original_mf->get_tlx_addr().chip; + m_raw_addr.sub_partition = m_original_mf->get_tlx_addr().sub_partition; + } } mem_fetch::~mem_fetch() { m_status = MEM_FETCH_DELETED; } diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index 71d8acd..e039846 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -76,6 +76,10 @@ class mem_fetch { void print(FILE *fp, bool print_inst = true) const; const addrdec_t &get_tlx_addr() const { return m_raw_addr; } + void set_chip(unsigned chip_id) { m_raw_addr.chip = chip_id; } + void set_parition(unsigned sub_partition_id) { + m_raw_addr.sub_partition = sub_partition_id; + } unsigned get_data_size() const { return m_data_size; } void set_data_size(unsigned size) { m_data_size = size; } unsigned get_ctrl_size() const { return m_ctrl_size; } diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index e50ad9e..63d7ee8 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -39,9 +39,11 @@ #include "stat-tool.h" #include "visualizer.h" +#include <math.h> #include <stdio.h> #include <stdlib.h> #include <string.h> + #include "../../libcuda/gpgpu_context.h" memory_stats_t::memory_stats_t(unsigned n_shader, @@ -226,14 +228,18 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) { bankwrites[mf->get_sid()][dram_id][bank]++; shader_mem_acc_log(mf->get_sid(), dram_id, bank, 'w'); } - totalbankwrites[dram_id][bank]++; + totalbankwrites[dram_id][bank] += + ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } else { bankreads[mf->get_sid()][dram_id][bank]++; shader_mem_acc_log(mf->get_sid(), dram_id, bank, 'r'); - totalbankreads[dram_id][bank]++; + totalbankreads[dram_id][bank] += + ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } - mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; + mem_access_type_stats[mf->get_access_type()][dram_id][bank] += + ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } + if (mf->get_pc() != (unsigned)-1) m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_dram_traffic( mf->get_pc(), mf->get_data_size()); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b596c0d..8b226b6 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -74,32 +74,38 @@ std::list<unsigned> shader_core_ctx::get_regs_written(const inst_t &fvt) const { return result; } -shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, - class simt_core_cluster *cluster, - unsigned shader_id, unsigned tpc_id, - const shader_core_config *config, - const memory_config *mem_config, - shader_core_stats *stats) - : core_t(gpu, NULL, config->warp_size, config->n_thread_per_shader), - m_barriers(this, config->max_warps_per_shader, config->max_cta_per_core, - config->max_barriers_per_cta, config->warp_size), - m_active_warps(0), - m_dynamic_warp_id(0) { - m_cluster = cluster; - m_config = config; - m_memory_config = mem_config; - m_stats = stats; - unsigned warp_size = config->warp_size; - Issue_Prio = 0; - - m_sid = shader_id; - m_tpc = tpc_id; +void exec_shader_core_ctx::create_shd_warp() { + m_warp.resize(m_config->max_warps_per_shader); + for (unsigned k = 0; k < m_config->max_warps_per_shader; ++k) { + m_warp[k] = new shd_warp_t(this, m_config->warp_size); + } +} - m_pipeline_reg.reserve(N_PIPELINE_STAGES); +void shader_core_ctx::create_front_pipeline() { + // pipeline_stages is the sum of normal pipeline stages and specialized_unit + // stages * 2 (for ID and EX) + unsigned total_pipeline_stages = + N_PIPELINE_STAGES + m_config->m_specialized_unit.size() * 2; + m_pipeline_reg.reserve(total_pipeline_stages); for (int j = 0; j < N_PIPELINE_STAGES; j++) { m_pipeline_reg.push_back( register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j])); } + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + m_pipeline_reg.push_back( + register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width, + m_config->m_specialized_unit[j].name)); + m_config->m_specialized_unit[j].ID_OC_SPEC_ID = m_pipeline_reg.size() - 1; + m_specilized_dispatch_reg.push_back( + &m_pipeline_reg[m_pipeline_reg.size() - 1]); + } + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + m_pipeline_reg.push_back( + register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width, + m_config->m_specialized_unit[j].name)); + m_config->m_specialized_unit[j].OC_EX_SPEC_ID = m_pipeline_reg.size() - 1; + } + if (m_config->sub_core_model) { // in subcore model, each scheduler should has its own issue register, so // num scheduler = reg width @@ -120,14 +126,14 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_pipeline_reg[ID_OC_INT].get_size()); } - m_threadState = - (thread_ctx_t *)calloc(sizeof(thread_ctx_t), config->n_thread_per_shader); + m_threadState = (thread_ctx_t *)calloc(sizeof(thread_ctx_t), + m_config->n_thread_per_shader); m_not_completed = 0; m_active_threads.reset(); m_n_active_cta = 0; for (unsigned i = 0; i < MAX_CTA_PER_SHADER; i++) m_cta_status[i] = 0; - for (unsigned i = 0; i < config->n_thread_per_shader; i++) { + for (unsigned i = 0; i < m_config->n_thread_per_shader; i++) { m_thread[i] = NULL; m_threadState[i].m_cta_id = -1; m_threadState[i].m_active = false; @@ -135,12 +141,12 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, // m_icnt = new shader_memory_interface(this,cluster); if (m_config->gpgpu_perfect_mem) { - m_icnt = new perfect_memory_interface(this, cluster); + m_icnt = new perfect_memory_interface(this, m_cluster); } else { - m_icnt = new shader_memory_interface(this, cluster); + m_icnt = new shader_memory_interface(this, m_cluster); } m_mem_fetch_allocator = - new shader_core_mem_fetch_allocator(shader_id, tpc_id, mem_config); + new shader_core_mem_fetch_allocator(m_sid, m_tpc, m_memory_config); // fetch m_last_warp_fetched = 0; @@ -151,9 +157,10 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_L1I = new read_only_cache(name, m_config->m_L1I_config, m_sid, get_shader_instruction_cache_id(), m_icnt, IN_L1I_MISS_QUEUE); +} - m_warp.resize(m_config->max_warps_per_shader, shd_warp_t(this, warp_size)); - m_scoreboard = new Scoreboard(m_sid, m_config->max_warps_per_shader, gpu); +void shader_core_ctx::create_schedulers() { + m_scoreboard = new Scoreboard(m_sid, m_config->max_warps_per_shader, m_gpu); // scedulers // must currently occur after all inputs have been initialized. @@ -180,37 +187,40 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE: schedulers.push_back(new two_level_active_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i, - config->gpgpu_scheduler_string)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string)); break; case CONCRETE_SCHEDULER_GTO: schedulers.push_back(new gto_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_OLDEST_FIRST: schedulers.push_back(new oldest_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i)); break; case CONCRETE_SCHEDULER_WARP_LIMITING: schedulers.push_back(new swl_scheduler( m_stats, this, m_scoreboard, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_INT], - &m_pipeline_reg[ID_OC_TENSOR_CORE], &m_pipeline_reg[ID_OC_MEM], i, - config->gpgpu_scheduler_string)); + &m_pipeline_reg[ID_OC_TENSOR_CORE], m_specilized_dispatch_reg, + &m_pipeline_reg[ID_OC_MEM], i, m_config->gpgpu_scheduler_string)); break; default: abort(); @@ -225,9 +235,10 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; ++i) { schedulers[i]->done_adding_supervised_warps(); } +} +void shader_core_ctx::create_exec_pipeline() { // op collector configuration - enum { SP_CUS, DP_CUS, SFU_CUS, TENSOR_CORE_CUS, INT_CUS, MEM_CUS, GEN_CUS }; opndcoll_rfu_t::port_vector_t in_ports; @@ -259,6 +270,14 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, in_ports.push_back(&m_pipeline_reg[ID_OC_INT]); out_ports.push_back(&m_pipeline_reg[OC_EX_INT]); } + if (m_config->m_specialized_unit.size() > 0) { + for (unsigned j = 0; j < m_config->m_specialized_unit.size(); ++j) { + in_ports.push_back( + &m_pipeline_reg[m_config->m_specialized_unit[j].ID_OC_SPEC_ID]); + out_ports.push_back( + &m_pipeline_reg[m_config->m_specialized_unit[j].OC_EX_SPEC_ID]); + } + } cu_sets.push_back((unsigned)GEN_CUS); m_operand_collector.add_port(in_ports, out_ports, cu_sets); in_ports.clear(), out_ports.clear(), cu_sets.clear(); @@ -272,8 +291,9 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp); m_operand_collector.add_cu_set( - TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, - config->gpgpu_operand_collector_num_out_ports_tensor_core); + TENSOR_CORE_CUS, + m_config->gpgpu_operand_collector_num_units_tensor_core, + m_config->gpgpu_operand_collector_num_out_ports_tensor_core); m_operand_collector.add_cu_set( SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); @@ -315,7 +335,7 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, } for (unsigned i = 0; - i < config->gpgpu_operand_collector_num_in_ports_tensor_core; i++) { + i < m_config->gpgpu_operand_collector_num_in_ports_tensor_core; i++) { in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]); out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]); cu_sets.push_back((unsigned)TENSOR_CORE_CUS); @@ -350,7 +370,7 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + m_config->gpgpu_num_tensor_core_units + - m_config->gpgpu_num_int_units + + m_config->gpgpu_num_int_units + m_config->m_specialized_unit_num + 1; // sp_unit, sfu, dp, tensor, int, ldst_unit // m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; // m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -380,15 +400,26 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_issue_port.push_back(OC_EX_SFU); } - for (int k = 0; k < config->gpgpu_num_tensor_core_units; k++) { + for (int k = 0; k < m_config->gpgpu_num_tensor_core_units; k++) { m_fu.push_back(new tensor_core(&m_pipeline_reg[EX_WB], m_config, this)); m_dispatch_port.push_back(ID_OC_TENSOR_CORE); m_issue_port.push_back(OC_EX_TENSOR_CORE); } - m_ldst_unit = - new ldst_unit(m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, - m_scoreboard, config, mem_config, stats, shader_id, tpc_id); + for (int j = 0; j < m_config->m_specialized_unit.size(); j++) { + for (unsigned k = 0; k < m_config->m_specialized_unit[j].num_units; k++) { + m_fu.push_back(new specialized_unit( + &m_pipeline_reg[EX_WB], m_config, this, SPEC_UNIT_START_ID + j, + m_config->m_specialized_unit[j].name, + m_config->m_specialized_unit[j].latency)); + m_dispatch_port.push_back(m_config->m_specialized_unit[j].ID_OC_SPEC_ID); + m_issue_port.push_back(m_config->m_specialized_unit[j].OC_EX_SPEC_ID); + } + } + + m_ldst_unit = new ldst_unit(m_icnt, m_mem_fetch_allocator, this, + &m_operand_collector, m_scoreboard, m_config, + m_memory_config, m_stats, m_sid, m_tpc); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); m_issue_port.push_back(OC_EX_MEM); @@ -398,10 +429,32 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_fu.size() == m_issue_port.size()); // there are as many result buses as the width of the EX_WB stage - num_result_bus = config->pipe_widths[EX_WB]; + num_result_bus = m_config->pipe_widths[EX_WB]; for (unsigned i = 0; i < num_result_bus; i++) { this->m_result_bus.push_back(new std::bitset<MAX_ALU_LATENCY>()); } +} + +shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, + class simt_core_cluster *cluster, + unsigned shader_id, unsigned tpc_id, + const shader_core_config *config, + const memory_config *mem_config, + shader_core_stats *stats) + : core_t(gpu, NULL, config->warp_size, config->n_thread_per_shader), + m_barriers(this, config->max_warps_per_shader, config->max_cta_per_core, + config->max_barriers_per_cta, config->warp_size), + m_active_warps(0), + m_dynamic_warp_id(0) { + m_cluster = cluster; + m_config = config; + m_memory_config = mem_config; + m_stats = stats; + unsigned warp_size = config->warp_size; + Issue_Prio = 0; + + m_sid = shader_id; + m_tpc = tpc_id; m_last_inst_gpu_sim_cycle = 0; m_last_inst_gpu_tot_sim_cycle = 0; @@ -436,15 +489,17 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, } for (unsigned i = start_thread / m_config->warp_size; i < end_thread / m_config->warp_size; ++i) { - m_warp[i].reset(); + m_warp[i]->reset(); m_simt_stack[i]->reset(); } } void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread, unsigned ctaid, - int cta_size, unsigned kernel_id) { + int cta_size, kernel_info_t &kernel) { + // address_type start_pc = next_pc(start_thread); + unsigned kernel_id = kernel.get_uid(); if (m_config->model == POST_DOMINATOR) { unsigned start_warp = start_thread / m_config->warp_size; unsigned warp_per_cta = cta_size / m_config->warp_size; @@ -473,13 +528,15 @@ void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, m_simt_stack[i]->resume(fname); m_simt_stack[i]->get_pdom_stack_top_info(&pc, &rpc); for (unsigned t = 0; t < m_config->warp_size; t++) { - m_thread[i * m_config->warp_size + t]->set_npc(pc); - m_thread[i * m_config->warp_size + t]->update_pc(); + if (m_thread != NULL) { + m_thread[i * m_config->warp_size + t]->set_npc(pc); + m_thread[i * m_config->warp_size + t]->update_pc(); + } } start_pc = pc; } - m_warp[i].init(start_pc, cta_id, i, active_threads, m_dynamic_warp_id); + m_warp[i]->init(start_pc, cta_id, i, active_threads, m_dynamic_warp_id); ++m_dynamic_warp_id; m_not_completed += n_active; ++m_active_warps; @@ -772,13 +829,32 @@ void shader_core_stats::visualizer_print(gzFile visualizer_file) { 0xF0000000 /* should be distinct from other memory spaces... \ check ptx_ir.h to verify this does not overlap \ other memory spaces */ + +const warp_inst_t *exec_shader_core_ctx::get_next_inst(unsigned warp_id, + address_type pc) { + // read the inst from the functional model + return m_gpu->gpgpu_ctx->ptx_fetch_inst(pc); +} + +void exec_shader_core_ctx::get_pdom_stack_top_info(unsigned warp_id, + const warp_inst_t *pI, + unsigned *pc, + unsigned *rpc) { + m_simt_stack[warp_id]->get_pdom_stack_top_info(pc, rpc); +} + +const active_mask_t &exec_shader_core_ctx::get_active_mask( + unsigned warp_id, const warp_inst_t *pI) { + return m_simt_stack[warp_id]->get_active_mask(); +} + void shader_core_ctx::decode() { if (m_inst_fetch_buffer.m_valid) { // decode 1 or 2 instructions and place them into ibuffer address_type pc = m_inst_fetch_buffer.m_pc; - const warp_inst_t *pI1 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc); - m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(0, pI1); - m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline(); + const warp_inst_t *pI1 = get_next_inst(m_inst_fetch_buffer.m_warp_id, pc); + m_warp[m_inst_fetch_buffer.m_warp_id]->ibuffer_fill(0, pI1); + m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline(); if (pI1) { m_stats->m_num_decoded_insn[m_sid]++; if (pI1->oprnd_type == INT_OP) { @@ -787,10 +863,10 @@ void shader_core_ctx::decode() { m_stats->m_num_FPdecoded_insn[m_sid]++; } const warp_inst_t *pI2 = - m_gpu->gpgpu_ctx->ptx_fetch_inst(pc + pI1->isize); + get_next_inst(m_inst_fetch_buffer.m_warp_id, pc + pI1->isize); if (pI2) { - m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1, pI2); - m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline(); + m_warp[m_inst_fetch_buffer.m_warp_id]->ibuffer_fill(1, pI2); + m_warp[m_inst_fetch_buffer.m_warp_id]->inc_inst_in_pipeline(); m_stats->m_num_decoded_insn[m_sid]++; if (pI2->oprnd_type == INT_OP) { m_stats->m_num_INTdecoded_insn[m_sid]++; @@ -807,15 +883,16 @@ void shader_core_ctx::fetch() { if (!m_inst_fetch_buffer.m_valid) { if (m_L1I->access_ready()) { mem_fetch *mf = m_L1I->next_access(); - m_warp[mf->get_wid()].clear_imiss_pending(); - m_inst_fetch_buffer = ifetch_buffer_t( - m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); - assert(m_warp[mf->get_wid()].get_pc() == + m_warp[mf->get_wid()]->clear_imiss_pending(); + m_inst_fetch_buffer = + ifetch_buffer_t(m_warp[mf->get_wid()]->get_pc(), + mf->get_access_size(), mf->get_wid()); + assert(m_warp[mf->get_wid()]->get_pc() == (mf->get_addr() - PROGRAM_MEM_START)); // Verify that we got the instruction we // were expecting. m_inst_fetch_buffer.m_valid = true; - m_warp[mf->get_wid()].set_last_fetch(m_gpu->gpu_sim_cycle); + m_warp[mf->get_wid()]->set_last_fetch(m_gpu->gpu_sim_cycle); delete mf; } else { // find an active warp with space in instruction buffer that is not @@ -827,33 +904,37 @@ void shader_core_ctx::fetch() { // this code checks if this warp has finished executing and can be // reclaimed - if (m_warp[warp_id].hardware_done() && + if (m_warp[warp_id]->hardware_done() && !m_scoreboard->pendingWrites(warp_id) && - !m_warp[warp_id].done_exit()) { + !m_warp[warp_id]->done_exit()) { bool did_exit = false; for (unsigned t = 0; t < m_config->warp_size; t++) { unsigned tid = warp_id * m_config->warp_size + t; if (m_threadState[tid].m_active == true) { m_threadState[tid].m_active = false; - unsigned cta_id = m_warp[warp_id].get_cta_id(); - register_cta_thread_exit(cta_id, &(m_thread[tid]->get_kernel())); + unsigned cta_id = m_warp[warp_id]->get_cta_id(); + if (m_thread[tid] == NULL) { + register_cta_thread_exit(cta_id, m_kernel); + } else { + register_cta_thread_exit(cta_id, + &(m_thread[tid]->get_kernel())); + } m_not_completed -= 1; m_active_threads.reset(tid); - assert(m_thread[tid] != NULL); did_exit = true; } } - if (did_exit) m_warp[warp_id].set_done_exit(); + if (did_exit) m_warp[warp_id]->set_done_exit(); --m_active_warps; assert(m_active_warps >= 0); } // this code fetches instructions from the i-cache or generates memory - // requests - if (!m_warp[warp_id].functional_done() && - !m_warp[warp_id].imiss_pending() && - m_warp[warp_id].ibuffer_empty()) { - address_type pc = m_warp[warp_id].get_pc(); + if (!m_warp[warp_id]->functional_done() && + !m_warp[warp_id]->imiss_pending() && + m_warp[warp_id]->ibuffer_empty()) { + address_type pc; + pc = m_warp[warp_id]->get_pc(); address_type ppc = pc + PROGRAM_MEM_START; unsigned nbytes = 16; unsigned offset_in_block = @@ -869,17 +950,22 @@ void shader_core_ctx::fetch() { warp_id, m_sid, m_tpc, m_memory_config, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); std::list<cache_event> events; - enum cache_request_status status = m_L1I->access( - (new_addr_type)ppc, mf, - m_gpu->gpu_sim_cycle + m_gpu->gpu_tot_sim_cycle, events); + enum cache_request_status status; + if (m_config->perfect_inst_const_cache) + status = HIT; + else + status = m_L1I->access( + (new_addr_type)ppc, mf, + m_gpu->gpu_sim_cycle + m_gpu->gpu_tot_sim_cycle, events); + if (status == MISS) { m_last_warp_fetched = warp_id; - m_warp[warp_id].set_imiss_pending(); - m_warp[warp_id].set_last_fetch(m_gpu->gpu_sim_cycle); + m_warp[warp_id]->set_imiss_pending(); + m_warp[warp_id]->set_last_fetch(m_gpu->gpu_sim_cycle); } else if (status == HIT) { m_last_warp_fetched = warp_id; m_inst_fetch_buffer = ifetch_buffer_t(pc, nbytes, warp_id); - m_warp[warp_id].set_last_fetch(m_gpu->gpu_sim_cycle); + m_warp[warp_id]->set_last_fetch(m_gpu->gpu_sim_cycle); delete mf; } else { m_last_warp_fetched = warp_id; @@ -895,7 +981,7 @@ void shader_core_ctx::fetch() { m_L1I->cycle(); } -void shader_core_ctx::func_exec_inst(warp_inst_t &inst) { +void exec_shader_core_ctx::func_exec_inst(warp_inst_t &inst) { execute_warp_inst_t(inst); if (inst.is_load() || inst.is_store()) { inst.generate_mem_accesses(); @@ -911,27 +997,29 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, pipe_reg_set.get_free(m_config->sub_core_model, sch_id); assert(pipe_reg); - m_warp[warp_id].ibuffer_free(); + m_warp[warp_id]->ibuffer_free(); assert(next_inst->valid()); **pipe_reg = *next_inst; // static instruction information (*pipe_reg)->issue(active_mask, warp_id, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle, - m_warp[warp_id].get_dynamic_warp_id(), + m_warp[warp_id]->get_dynamic_warp_id(), sch_id); // dynamic instruction information m_stats->shader_cycle_distro[2 + (*pipe_reg)->active_count()]++; func_exec_inst(**pipe_reg); + if (next_inst->op == BARRIER_OP) { - m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); - m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(), warp_id, + m_warp[warp_id]->store_info_of_last_inst_at_barrier(*pipe_reg); + m_barriers.warp_reaches_barrier(m_warp[warp_id]->get_cta_id(), warp_id, const_cast<warp_inst_t *>(next_inst)); } else if (next_inst->op == MEMORY_BARRIER_OP) { - m_warp[warp_id].set_membar(); + m_warp[warp_id]->set_membar(); } updateSIMTStack(warp_id, *pipe_reg); + m_scoreboard->reserveRegisters(*pipe_reg); - m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize); + m_warp[warp_id]->set_next_pc(next_inst->pc + next_inst->isize); } void shader_core_ctx::issue() { @@ -949,7 +1037,7 @@ void shader_core_ctx::issue() { //} } -shd_warp_t &scheduler_unit::warp(int i) { return (*m_warp)[i]; } +shd_warp_t &scheduler_unit::warp(int i) { return *((*m_warp)[i]); } /** * A general function to order things in a Loose Round Robin way. The simplist @@ -1068,6 +1156,17 @@ void scheduler_unit::cycle() { // units (as in Maxwell and // Pascal) + if (warp(warp_id).ibuffer_empty()) + SCHED_DPRINTF( + "Warp (warp_id %u, dynamic_warp_id %u) fails as ibuffer_empty\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id()); + + if (warp(warp_id).waiting()) + SCHED_DPRINTF( + "Warp (warp_id %u, dynamic_warp_id %u) fails as waiting for " + "barrier\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id()); + while (!warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue)) { @@ -1082,7 +1181,7 @@ void scheduler_unit::cycle() { bool valid = warp(warp_id).ibuffer_next_valid(); bool warp_inst_issued = false; unsigned pc, rpc; - m_simt_stack[warp_id]->get_pdom_stack_top_info(&pc, &rpc); + m_shader->get_pdom_stack_top_info(warp_id, pI, &pc, &rpc); SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) has valid instruction (%s)\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id(), @@ -1105,8 +1204,10 @@ void scheduler_unit::cycle() { "Warp (warp_id %u, dynamic_warp_id %u) passes scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id()); ready_inst = true; + const active_mask_t &active_mask = - m_simt_stack[warp_id]->get_active_mask(); + m_shader->get_active_mask(warp_id, pI); + assert(warp(warp_id).inst_in_pipeline()); if ((pI->op == LOAD_OP) || (pI->op == STORE_OP) || @@ -1126,19 +1227,25 @@ void scheduler_unit::cycle() { } } else { bool sp_pipe_avail = + (m_shader->m_config->gpgpu_num_sp_units > 0) && m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id); bool sfu_pipe_avail = + (m_shader->m_config->gpgpu_num_sfu_units > 0) && m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool tensor_core_pipe_avail = m_tensor_core_out->has_free( - m_shader->m_config->sub_core_model, m_id); + bool tensor_core_pipe_avail = + (m_shader->m_config->gpgpu_num_tensor_core_units > 0) && + m_tensor_core_out->has_free( + m_shader->m_config->sub_core_model, m_id); bool dp_pipe_avail = + (m_shader->m_config->gpgpu_num_dp_units > 0) && m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id); bool int_pipe_avail = + (m_shader->m_config->gpgpu_num_int_units > 0) && m_int_out->has_free(m_shader->m_config->sub_core_model, m_id); // This code need to be refactored if (pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && - pI->op != DP_OP) { + pI->op != DP_OP && !(pI->op >= SPEC_UNIT_START_ID)) { bool execute_on_SP = false; bool execute_on_INT = false; @@ -1227,7 +1334,7 @@ void scheduler_unit::cycle() { } } else if ((pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == - exec_unit_type_t::SP)) { + exec_unit_type_t::TENSOR)) { if (tensor_core_pipe_avail) { m_shader->issue_warp(*m_tensor_core_out, pI, active_mask, warp_id, m_id); @@ -1236,7 +1343,30 @@ void scheduler_unit::cycle() { warp_inst_issued = true; previous_issued_inst_exec_type = exec_unit_type_t::TENSOR; } + } else if ((pI->op >= SPEC_UNIT_START_ID) && + !(diff_exec_units && + previous_issued_inst_exec_type == + exec_unit_type_t::SPECIALIZED)) { + unsigned spec_id = pI->op - SPEC_UNIT_START_ID; + assert(spec_id < m_shader->m_config->m_specialized_unit.size()); + register_set *spec_reg_set = m_spec_cores_out[spec_id]; + bool spec_pipe_avail = + (m_shader->m_config->m_specialized_unit[spec_id].num_units > + 0) && + spec_reg_set->has_free(m_shader->m_config->sub_core_model, + m_id); + + if (spec_pipe_avail) { + m_shader->issue_warp(*spec_reg_set, pI, active_mask, warp_id, + m_id); + issued++; + issued_inst = true; + warp_inst_issued = true; + previous_issued_inst_exec_type = + exec_unit_type_t::SPECIALIZED; + } } + } // end of else } else { SCHED_DPRINTF( @@ -1405,13 +1535,15 @@ void two_level_active_scheduler::order_warps() { swl_scheduler::swl_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id, char *config_string) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) { + sfu_out, int_out, tensor_core_out, spec_cores_out, mem_out, + id) { unsigned m_prioritization_readin; int ret = sscanf(config_string, "warp_limiting:%d:%d", &m_prioritization_readin, &m_num_warps_to_limit); @@ -1533,7 +1665,7 @@ void shader_core_ctx::execute() { unsigned multiplier = m_fu[n]->clock_multiplier(); for (unsigned c = 0; c < multiplier; c++) m_fu[n]->cycle(); m_fu[n]->active_lanes_in_pipeline(); - enum pipeline_stage_name_t issue_port = m_issue_port[n]; + unsigned issue_port = m_issue_port[n]; register_set &issue_inst = m_pipeline_reg[issue_port]; warp_inst_t **ready_reg = issue_inst.get_ready(); if (issue_inst.has_ready() && m_fu[n]->can_issue(**ready_reg)) { @@ -1579,8 +1711,8 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const { void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst) { #if 0 - printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", - inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); + printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu \n", + inst.get_uid(), m_sid, inst.warp_id(), inst.pc, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); #endif if (inst.op_pipe == SP__OP) @@ -1635,7 +1767,7 @@ void shader_core_ctx::writeback() { m_operand_collector.writeback(*pipe_reg); unsigned warp_id = pipe_reg->warp_id(); m_scoreboard->releaseRegisters(pipe_reg); - m_warp[warp_id].dec_inst_in_pipeline(); + m_warp[warp_id]->dec_inst_in_pipeline(); warp_inst_complete(*pipe_reg); m_gpu->gpu_sim_insn_last_update_sid = m_sid; m_gpu->gpu_sim_insn_last_update = m_gpu->gpu_sim_cycle; @@ -1651,6 +1783,8 @@ bool ldst_unit::shared_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) { if (inst.space.get_type() != shared_space) return true; + if (inst.active_count() == 0) return true; + if (inst.has_dispatch_delay()) { m_stats->gpgpu_n_shmem_bank_access[m_sid]++; } @@ -1852,7 +1986,19 @@ bool ldst_unit::constant_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail, (inst.space.get_type() != param_space_kernel))) return true; if (inst.active_count() == 0) return true; - mem_stage_stall_type fail = process_memory_access_queue(m_L1C, inst); + + mem_stage_stall_type fail; + if (m_config->perfect_inst_const_cache) { + fail = NO_RC_FAIL; + while (inst.accessq_count() > 0) inst.accessq_pop_back(); + if (inst.is_load()) { + for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) + if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]]--; + } + } else { + fail = process_memory_access_queue(m_L1C, inst); + } + if (fail != NO_RC_FAIL) { rc_fail = fail; // keep other fails if this didn't fail. fail_type = C_MEM; @@ -1885,7 +2031,8 @@ bool ldst_unit::memory_cycle(warp_inst_t &inst, (inst.space.get_type() != param_space_local))) return true; if (inst.active_count() == 0) return true; - assert(!inst.accessq_empty()); + if (inst.accessq_empty()) return true; + mem_stage_stall_type stall_cond = NO_RC_FAIL; const mem_access_t &access = inst.accessq_back(); @@ -2027,6 +2174,13 @@ void dp_unit::active_lanes_in_pipeline() { m_core->incfuactivelanes_stat(active_count); m_core->incfumemactivelanes_stat(active_count); } +void specialized_unit::active_lanes_in_pipeline() { + unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline(); + assert(active_count <= m_core->get_config()->warp_size); + m_core->incspactivelanes_stat(active_count); + m_core->incfuactivelanes_stat(active_count); + m_core->incfumemactivelanes_stat(active_count); +} void int_unit::active_lanes_in_pipeline() { unsigned active_count = pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -2057,6 +2211,15 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config, m_name = "SP "; } +specialized_unit::specialized_unit(register_set *result_port, + const shader_core_config *config, + shader_core_ctx *core, unsigned supported_op, + char *unit_name, unsigned latency) + : pipelined_simd_unit(result_port, config, latency, core) { + m_name = unit_name; + m_supported_op = supported_op; +} + dp_unit::dp_unit(register_set *result_port, const shader_core_config *config, shader_core_ctx *core) : pipelined_simd_unit(result_port, config, config->max_dp_latency, core) { @@ -2085,6 +2248,14 @@ void dp_unit ::issue(register_set &source_reg) { pipelined_simd_unit::issue(source_reg); } +void specialized_unit ::issue(register_set &source_reg) { + warp_inst_t **ready_reg = source_reg.get_ready(); + // m_core->incexecstat((*ready_reg)); + (*ready_reg)->op_pipe = SPECIALIZED__OP; + m_core->incsp_stat(m_core->get_config()->warp_size, (*ready_reg)->latency); + pipelined_simd_unit::issue(source_reg); +} + void int_unit ::issue(register_set &source_reg) { warp_inst_t **ready_reg = source_reg.get_ready(); // m_core->incexecstat((*ready_reg)); @@ -2316,10 +2487,11 @@ void ldst_unit::writeback() { case 3: // global/local if (m_next_global) { m_next_wb = m_next_global->get_inst(); - if (m_next_global->isatomic()) + if (m_next_global->isatomic()) { m_core->decrement_atomic_count( m_next_global->get_wid(), m_next_global->get_access_warp_mask().count()); + } delete m_next_global; m_next_global = NULL; serviced_client = next_client; @@ -2376,7 +2548,8 @@ inst->space.get_type() != shared_space) { unsigned warp_id = inst->warp_id(); */ void ldst_unit::cycle() { writeback(); - m_operand_collector->step(); + for (int i = 0; i < m_config->reg_file_port_throughput; ++i) + m_operand_collector->step(); for (unsigned stage = 0; (stage + 1) < m_pipeline_depth; stage++) if (m_pipeline_reg[stage]->empty() && !m_pipeline_reg[stage + 1]->empty()) move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage + 1]); @@ -2954,7 +3127,7 @@ void shader_core_ctx::display_pipeline(FILE *fout, int print_mem, } fprintf(fout, "\nibuffer status:\n"); for (unsigned i = 0; i < m_config->max_warps_per_shader; i++) { - if (!m_warp[i].ibuffer_empty()) m_warp[i].print_ibuffer(fout); + if (!m_warp[i]->ibuffer_empty()) m_warp[i]->print_ibuffer(fout); } fprintf(fout, "\n"); display_simt_state(fout, mask); @@ -3095,11 +3268,11 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { switch (adaptive_cache_config) { case FIXED: break; - case VOLTA: { + case ADAPTIVE_VOLTA: { // For Volta, we assign the remaining shared memory to L1 cache // For more info about adaptive cache, see // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - assert(gpgpu_shmem_size == 98304); // Volta has 96 KB shared + // assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared // To Do: make it flexible and not tuned to 9KB share memory unsigned max_assoc = m_L1D_config.get_max_assoc(); @@ -3184,8 +3357,10 @@ void shader_core_ctx::cycle() { execute(); read_operands(); issue(); - decode(); - fetch(); + for (int i = 0; i < m_config->inst_fetch_throughput; ++i) { + decode(); + fetch(); + } } // Flushes all content of the cache to memory @@ -3234,28 +3409,34 @@ std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads() { ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix + // printf("####\n"); for (int p = 0; p < _square; ++p) { - output = (_pri + p) % _square; + output = (_pri + p) % _outputs; // Step through the current diagonal for (input = 0; input < _inputs; ++input) { assert(input < _inputs); assert(output < _outputs); if ((output < _outputs) && (_inmatch[input] == -1) && - (_outmatch[output] == -1) && + //( _outmatch[output] == -1 ) && //allow OC to read multiple reg + // banks at the same cycle (_request[input][output] /*.label != -1*/)) { // Grant! _inmatch[input] = output; _outmatch[output] = input; + // printf("Register File: granting bank %d to OC %d, schedid %d, warpid + // %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), + // (m_queue[input].front()).get_wid(), + // (m_queue[input].front()).get_reg()); } - output = (output + 1) % _square; + output = (output + 1) % _outputs; } } // Round-robin the priority diagonal - _pri = (_pri + 1) % _square; + _pri = (_pri + 1) % _outputs; /// <--- end code from booksim @@ -3466,7 +3647,7 @@ bool shader_core_ctx::check_if_non_released_reduction_barrier( bool non_released_barrier_reduction = false; bool warp_stucked_at_barrier = warp_waiting_at_barrier(warp_id); bool single_inst_in_pipeline = - (m_warp[warp_id].num_issued_inst_in_pipeline() == 1); + (m_warp[warp_id]->num_issued_inst_in_pipeline() == 1); non_released_barrier_reduction = single_inst_in_pipeline and warp_stucked_at_barrier and bar_red_op; printf("non_released_barrier_reduction=%u\n", non_released_barrier_reduction); @@ -3478,9 +3659,18 @@ bool shader_core_ctx::warp_waiting_at_barrier(unsigned warp_id) const { } bool shader_core_ctx::warp_waiting_at_mem_barrier(unsigned warp_id) { - if (!m_warp[warp_id].get_membar()) return false; + if (!m_warp[warp_id]->get_membar()) return false; if (!m_scoreboard->pendingWrites(warp_id)) { - m_warp[warp_id].clear_membar(); + m_warp[warp_id]->clear_membar(); + if (m_gpu->get_config().flush_l1()) { + // Mahmoud fixed this on Nov 2019 + // Invalidate L1 cache + // Based on Nvidia Doc, at MEM barrier, we have to + //(1) wait for all pending writes till they are acked + //(2) invalidate L1 cache to ensure coherence and avoid reading stall data + cache_invalidate(); + // TO DO: you need to stall the SM for 5k cycles. + } return false; } return true; @@ -3497,8 +3687,8 @@ void shader_core_ctx::set_max_cta(const kernel_info_t &kernel) { } void shader_core_ctx::decrement_atomic_count(unsigned wid, unsigned n) { - assert(m_warp[wid].get_n_atomic() >= n); - m_warp[wid].dec_n_atomic(n); + assert(m_warp[wid]->get_n_atomic() >= n); + m_warp[wid]->dec_n_atomic(n); } void shader_core_ctx::broadcast_barrier_reduction(unsigned cta_id, @@ -3507,7 +3697,7 @@ void shader_core_ctx::broadcast_barrier_reduction(unsigned cta_id, for (unsigned i = 0; i < m_config->max_warps_per_shader; i++) { if (warps.test(i)) { const warp_inst_t *inst = - m_warp[i].restore_info_of_last_inst_at_barrier(); + m_warp[i]->restore_info_of_last_inst_at_barrier(); const_cast<warp_inst_t *>(inst)->broadcast_barrier_reduction( inst->get_active_mask()); } @@ -3534,7 +3724,7 @@ void shader_core_ctx::store_ack(class mem_fetch *mf) { assert(mf->get_type() == WRITE_ACK || (m_config->gpgpu_perfect_mem && mf->get_is_write())); unsigned warp_id = mf->get_wid(); - m_warp[warp_id].dec_store_req(); + m_warp[warp_id]->dec_store_req(); } void shader_core_ctx::print_cache_stats(FILE *fp, unsigned &dl1_accesses, @@ -3910,6 +4100,16 @@ void opndcoll_rfu_t::collector_unit_t::dispatch() { for (unsigned i = 0; i < MAX_REG_OPERANDS * 2; i++) m_src_op[i].reset(); } +void exec_simt_core_cluster::create_shader_core_ctx() { + m_core = new shader_core_ctx *[m_config->n_simt_cores_per_cluster]; + for (unsigned i = 0; i < m_config->n_simt_cores_per_cluster; i++) { + unsigned sid = m_config->cid_to_sid(i, m_cluster_id); + m_core[i] = new exec_shader_core_ctx(m_gpu, this, sid, m_cluster_id, + m_config, m_mem_config, m_stats); + m_core_sim_order.push_back(i); + } +} + simt_core_cluster::simt_core_cluster(class gpgpu_sim *gpu, unsigned cluster_id, const shader_core_config *config, const memory_config *mem_config, @@ -3922,13 +4122,7 @@ simt_core_cluster::simt_core_cluster(class gpgpu_sim *gpu, unsigned cluster_id, m_gpu = gpu; m_stats = stats; m_memory_stats = mstats; - m_core = new shader_core_ctx *[config->n_simt_cores_per_cluster]; - for (unsigned i = 0; i < config->n_simt_cores_per_cluster; i++) { - unsigned sid = m_config->cid_to_sid(i, m_cluster_id); - m_core[i] = new shader_core_ctx(gpu, this, sid, m_cluster_id, config, - mem_config, stats); - m_core_sim_order.push_back(i); - } + m_mem_config = mem_config; } void simt_core_cluster::core_cycle() { @@ -4240,9 +4434,10 @@ void simt_core_cluster::get_L1T_sub_stats(struct cache_sub_stats &css) const { css = total_css; } -void shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t &inst, - unsigned t, unsigned tid) { - if (inst.isatomic()) m_warp[inst.warp_id()].inc_n_atomic(); +void exec_shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t &inst, + unsigned t, + unsigned tid) { + if (inst.isatomic()) m_warp[inst.warp_id()]->inc_n_atomic(); if (inst.space.is_local() && (inst.is_load() || inst.is_store())) { new_addr_type localaddrs[MAX_ACCESSES_PER_INSN_PER_THREAD]; unsigned num_addrs; @@ -4253,8 +4448,8 @@ void shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t &inst, inst.set_addr(t, (new_addr_type *)localaddrs, num_addrs); } if (ptx_thread_done(tid)) { - m_warp[inst.warp_id()].set_completed(t); - m_warp[inst.warp_id()].ibuffer_flush(); + m_warp[inst.warp_id()]->set_completed(t); + m_warp[inst.warp_id()]->ibuffer_flush(); } // PC-Histogram Update diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1af35cf..07cd2d0 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -79,7 +79,8 @@ enum exec_unit_type_t { MEM = 3, DP = 4, INT = 5, - TENSOR = 6 + TENSOR = 6, + SPECIALIZED = 7 }; class thread_ctx_t { @@ -167,7 +168,7 @@ class shd_warp_t { void set_membar() { m_membar = true; } void clear_membar() { m_membar = false; } bool get_membar() const { return m_membar; } - address_type get_pc() const { return m_next_pc; } + virtual address_type get_pc() const { return m_next_pc; } void set_next_pc(address_type pc) { m_next_pc = pc; } void store_info_of_last_inst_at_barrier(const warp_inst_t *pI) { @@ -326,9 +327,10 @@ class scheduler_unit { // this can be copied freely, so can be used in std public: scheduler_unit(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, register_set *sp_out, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id) : m_supervised_warps(), m_stats(stats), @@ -341,6 +343,7 @@ class scheduler_unit { // this can be copied freely, so can be used in std m_sfu_out(sfu_out), m_int_out(int_out), m_tensor_core_out(tensor_core_out), + m_spec_cores_out(spec_cores_out), m_mem_out(mem_out), m_id(id) {} virtual ~scheduler_unit() {} @@ -415,13 +418,14 @@ class scheduler_unit { // this can be copied freely, so can be used in std Scoreboard *m_scoreboard; simt_stack **m_simt_stack; // warp_inst_t** m_pipeline_reg; - std::vector<shd_warp_t> *m_warp; + std::vector<shd_warp_t *> *m_warp; register_set *m_sp_out; register_set *m_dp_out; register_set *m_sfu_out; register_set *m_int_out; register_set *m_tensor_core_out; register_set *m_mem_out; + std::vector<register_set *> &m_spec_cores_out; int m_id; }; @@ -430,12 +434,14 @@ class lrr_scheduler : public scheduler_unit { public: lrr_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, register_set *sp_out, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~lrr_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -447,12 +453,14 @@ class gto_scheduler : public scheduler_unit { public: gto_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, register_set *sp_out, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~gto_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -464,12 +472,14 @@ class oldest_scheduler : public scheduler_unit { public: oldest_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, register_set *sp_out, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id) {} + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id) {} virtual ~oldest_scheduler() {} virtual void order_warps(); virtual void done_adding_supervised_warps() { @@ -481,13 +491,15 @@ class two_level_active_scheduler : public scheduler_unit { public: two_level_active_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id, char *config_str) : scheduler_unit(stats, shader, scoreboard, simt, warp, sp_out, dp_out, - sfu_out, int_out, tensor_core_out, mem_out, id), + sfu_out, int_out, tensor_core_out, spec_cores_out, + mem_out, id), m_pending_warps() { unsigned inner_level_readin; unsigned outer_level_readin; @@ -530,9 +542,10 @@ class swl_scheduler : public scheduler_unit { public: swl_scheduler(shader_core_stats *stats, shader_core_ctx *shader, Scoreboard *scoreboard, simt_stack **simt, - std::vector<shd_warp_t> *warp, register_set *sp_out, + std::vector<shd_warp_t *> *warp, register_set *sp_out, register_set *dp_out, register_set *sfu_out, register_set *int_out, register_set *tensor_core_out, + std::vector<register_set *> &spec_cores_out, register_set *mem_out, int id, char *config_string); virtual ~swl_scheduler() {} virtual void order_warps(); @@ -1211,6 +1224,24 @@ class sp_unit : public pipelined_simd_unit { virtual void issue(register_set &source_reg); }; +class specialized_unit : public pipelined_simd_unit { + public: + specialized_unit(register_set *result_port, const shader_core_config *config, + shader_core_ctx *core, unsigned supported_op, + char *unit_name, unsigned latency); + virtual bool can_issue(const warp_inst_t &inst) const { + if (inst.op != m_supported_op) { + return false; + } + return pipelined_simd_unit::can_issue(inst); + } + virtual void active_lanes_in_pipeline(); + virtual void issue(register_set &source_reg); + + private: + unsigned m_supported_op; +}; + class simt_core_cluster; class shader_memory_interface; class shader_core_mem_fetch_allocator; @@ -1361,6 +1392,16 @@ const char *const pipeline_stage_name_decode[] = { "OC_EX_SFU", "OC_EX_MEM", "EX_WB", "ID_OC_TENSOR_CORE", "OC_EX_TENSOR_CORE", "N_PIPELINE_STAGES"}; +struct specialized_unit_params { + unsigned latency; + unsigned num_units; + unsigned id_oc_spec_reg_width; + unsigned oc_ex_spec_reg_width; + char name[20]; + unsigned ID_OC_SPEC_ID; + unsigned OC_EX_SPEC_ID; +}; + class shader_core_config : public core_config { public: shader_core_config(gpgpu_context *ctx) : core_config(ctx) { @@ -1419,6 +1460,24 @@ class shader_core_config : public core_config { gpgpu_cache_texl1_linesize = m_L1T_config.get_line_sz(); gpgpu_cache_constl1_linesize = m_L1C_config.get_line_sz(); m_valid = true; + + m_specialized_unit_num = 0; + // parse the specialized units + for (unsigned i = 0; i < SPECIALIZED_UNIT_NUM; ++i) { + unsigned enabled; + specialized_unit_params sparam; + sscanf(specialized_unit_string[i], "%u,%u,%u,%u,%u,%s", &enabled, + &sparam.num_units, &sparam.latency, &sparam.id_oc_spec_reg_width, + &sparam.oc_ex_spec_reg_width, sparam.name); + + if (enabled) { + m_specialized_unit.push_back(sparam); + strncpy(m_specialized_unit.back().name, sparam.name, + sizeof(m_specialized_unit.back().name)); + m_specialized_unit_num += sparam.num_units; + } else + break; // we only accept continuous specialized_units, i.e., 1,2,3,4 + } } void reg_options(class OptionParser *opp); unsigned max_cta(const kernel_info_t &k) const; @@ -1531,7 +1590,14 @@ class shader_core_config : public core_config { // Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; - bool adpative_volta_cache_config; + bool perfect_inst_const_cache; + unsigned inst_fetch_throughput; + unsigned reg_file_port_throughput; + + // specialized unit config strings + char *specialized_unit_string[SPECIALIZED_UNIT_NUM]; + mutable std::vector<specialized_unit_params> m_specialized_unit; + unsigned m_specialized_unit_num; }; struct shader_core_stats_pod { @@ -1860,9 +1926,9 @@ class shader_core_ctx : public core_t { // modifiers void mem_instruction_stats(const warp_inst_t &inst); void decrement_atomic_count(unsigned wid, unsigned n); - void inc_store_req(unsigned warp_id) { m_warp[warp_id].inc_store_req(); } + void inc_store_req(unsigned warp_id) { m_warp[warp_id]->inc_store_req(); } void dec_inst_in_pipeline(unsigned warp_id) { - m_warp[warp_id].dec_inst_in_pipeline(); + m_warp[warp_id]->dec_inst_in_pipeline(); } // also used in writeback() void store_ack(class mem_fetch *mf); bool warp_waiting_at_mem_barrier(unsigned warp_id); @@ -2041,7 +2107,7 @@ class shader_core_ctx : public core_t { } bool check_if_non_released_reduction_barrier(warp_inst_t &inst); - private: + protected: unsigned inactive_lanes_accesses_sfu(unsigned active_count, double latency) { return (((32 - active_count) >> 1) * latency) + (((32 - active_count) >> 3) * latency) + @@ -2053,10 +2119,6 @@ class shader_core_ctx : public core_t { } int test_res_bus(int latency); - void init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread, - unsigned ctaid, int cta_size, unsigned kernel_id); - virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, - unsigned tid); address_type next_pc(int tid) const; void fetch(); void register_cta_thread_exit(unsigned cta_num, kernel_info_t *kernel); @@ -2070,7 +2132,35 @@ class shader_core_ctx : public core_t { void issue_warp(register_set &warp, const warp_inst_t *pI, const active_mask_t &active_mask, unsigned warp_id, unsigned sch_id); - void func_exec_inst(warp_inst_t &inst); + + void create_front_pipeline(); + void create_schedulers(); + void create_exec_pipeline(); + + // pure virtual methods implemented based on the current execution mode + // (execution-driven vs trace-driven) + virtual void init_warps(unsigned cta_id, unsigned start_thread, + unsigned end_thread, unsigned ctaid, int cta_size, + kernel_info_t &kernel); + virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, + unsigned tid) = 0; + virtual void func_exec_inst(warp_inst_t &inst) = 0; + + virtual unsigned sim_init_thread(kernel_info_t &kernel, + ptx_thread_info **thread_info, int sid, + unsigned tid, unsigned threads_left, + unsigned num_threads, core_t *core, + unsigned hw_cta_id, unsigned hw_warp_id, + gpgpu_t *gpu) = 0; + + virtual void create_shd_warp() = 0; + + virtual const warp_inst_t *get_next_inst(unsigned warp_id, + address_type pc) = 0; + virtual void get_pdom_stack_top_info(unsigned warp_id, const warp_inst_t *pI, + unsigned *pc, unsigned *rpc) = 0; + virtual const active_mask_t &get_active_mask(unsigned warp_id, + const warp_inst_t *pI) = 0; // Returns numbers of addresses in translated_addrs unsigned translate_local_memaddr(address_type localaddr, unsigned tid, @@ -2086,6 +2176,7 @@ class shader_core_ctx : public core_t { // used in display_pipeline(): void dump_warp_state(FILE *fout) const; void print_stage(unsigned int stage, FILE *fout) const; + unsigned long long m_last_inst_gpu_sim_cycle; unsigned long long m_last_inst_gpu_tot_sim_cycle; @@ -2120,13 +2211,14 @@ class shader_core_ctx : public core_t { int m_last_warp_fetched; // decode/dispatch - std::vector<shd_warp_t> m_warp; // per warp information array + std::vector<shd_warp_t *> m_warp; // per warp information array barrier_set_t m_barriers; ifetch_buffer_t m_inst_fetch_buffer; std::vector<register_set> m_pipeline_reg; Scoreboard *m_scoreboard; opndcoll_rfu_t m_operand_collector; int m_active_warps; + std::vector<register_set *> m_specilized_dispatch_reg; // schedule std::vector<scheduler_unit *> schedulers; @@ -2136,8 +2228,8 @@ class shader_core_ctx : public core_t { // execute unsigned m_num_function_units; - std::vector<pipeline_stage_name_t> m_dispatch_port; - std::vector<pipeline_stage_name_t> m_issue_port; + std::vector<unsigned> m_dispatch_port; + std::vector<unsigned> m_issue_port; std::vector<simd_function_unit *> m_fu; // stallable pipelines should be last in this array ldst_unit *m_ldst_unit; @@ -2170,6 +2262,38 @@ class shader_core_ctx : public core_t { std::map<unsigned int, unsigned int> m_occupied_cta_to_hwtid; }; +class exec_shader_core_ctx : public shader_core_ctx { + public: + exec_shader_core_ctx(class gpgpu_sim *gpu, class simt_core_cluster *cluster, + unsigned shader_id, unsigned tpc_id, + const shader_core_config *config, + const memory_config *mem_config, + shader_core_stats *stats) + : shader_core_ctx(gpu, cluster, shader_id, tpc_id, config, mem_config, + stats) { + create_front_pipeline(); + create_shd_warp(); + create_schedulers(); + create_exec_pipeline(); + } + + virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, + unsigned tid); + virtual void func_exec_inst(warp_inst_t &inst); + virtual unsigned sim_init_thread(kernel_info_t &kernel, + ptx_thread_info **thread_info, int sid, + unsigned tid, unsigned threads_left, + unsigned num_threads, core_t *core, + unsigned hw_cta_id, unsigned hw_warp_id, + gpgpu_t *gpu); + virtual void create_shd_warp(); + virtual const warp_inst_t *get_next_inst(unsigned warp_id, address_type pc); + virtual void get_pdom_stack_top_info(unsigned warp_id, const warp_inst_t *pI, + unsigned *pc, unsigned *rpc); + virtual const active_mask_t &get_active_mask(unsigned warp_id, + const warp_inst_t *pI); +}; + class simt_core_cluster { public: simt_core_cluster(class gpgpu_sim *gpu, unsigned cluster_id, @@ -2217,20 +2341,36 @@ class simt_core_cluster { void get_icnt_stats(long &n_simt_to_mem, long &n_mem_to_simt) const; float get_current_occupancy(unsigned long long &active, unsigned long long &total) const; + virtual void create_shader_core_ctx() = 0; - private: + protected: unsigned m_cluster_id; gpgpu_sim *m_gpu; const shader_core_config *m_config; shader_core_stats *m_stats; memory_stats_t *m_memory_stats; shader_core_ctx **m_core; + const memory_config *m_mem_config; unsigned m_cta_issue_next_core; std::list<unsigned> m_core_sim_order; std::list<mem_fetch *> m_response_fifo; }; +class exec_simt_core_cluster : public simt_core_cluster { + public: + exec_simt_core_cluster(class gpgpu_sim *gpu, unsigned cluster_id, + const shader_core_config *config, + const memory_config *mem_config, + class shader_core_stats *stats, + class memory_stats_t *mstats) + : simt_core_cluster(gpu, cluster_id, config, mem_config, stats, mstats) { + create_shader_core_ctx(); + } + + virtual void create_shader_core_ctx(); +}; + class shader_memory_interface : public mem_fetch_interface { public: shader_memory_interface(shader_core_ctx *core, simt_core_cluster *cluster) { diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index b7b7f34..f4287d8 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -219,7 +219,7 @@ gpgpu_sim *gpgpu_context::gpgpu_ptx_sim_init_perf() { the_gpgpusim->g_the_gpu_config->init(); the_gpgpusim->g_the_gpu = - new gpgpu_sim(*(the_gpgpusim->g_the_gpu_config), this); + new exec_gpgpu_sim(*(the_gpgpusim->g_the_gpu_config), this); the_gpgpusim->g_stream_manager = new stream_manager( (the_gpgpusim->g_the_gpu), func_sim->g_cuda_launch_blocking); diff --git a/travis.sh b/travis.sh new file mode 100755 index 0000000..bbdd19a --- /dev/null +++ b/travis.sh @@ -0,0 +1,24 @@ +if [ ! -n "$CUDA_INSTALL_PATH" ]; then + echo "ERROR ** Install CUDA Toolkit and set CUDA_INSTALL_PATH."; + exit; +fi + +if [ ! -n "$CONFIG" ]; then + echo "ERROR ** set the CONFIG env variable to one of those found in ./accel-sim-framework/util/job_launching/configs/define-standard-cfgs.yml"; + exit; +fi + +if [ ! -n "$GPUAPPS_ROOT" ]; then + echo "ERROR ** GPUAPPS_ROOT to a location where the apps have been compiled"; + exit; +fi + +export PATH=$CUDA_INSTALL_PATH/bin:$PATH +source ./setup_environment +make -j + +pip install psutil +rm -rf accel-sim-framework +git clone https://github.com/accel-sim/accel-sim-framework.git +./accel-sim-framework/util/job_launching/run_simulations.py -C $CONFIG -B rodinia_2.0-ft -N regress -l local +./accel-sim-framework/util/job_launching/monitor_func_test.py -v -N regress -j procman |