diff options
| -rw-r--r-- | Jenkinsfile | 4 | ||||
| -rw-r--r-- | configs/3.x-cfgs/SM6_TITANX/gpgpusim.config | 1 | ||||
| -rw-r--r-- | configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 6 | ||||
| -rw-r--r-- | src/abstract_hardware_model.h | 1 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 1 | ||||
| -rw-r--r-- | src/cuda-sim/ptx_ir.cc | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 2 |
7 files changed, 10 insertions, 6 deletions
diff --git a/Jenkinsfile b/Jenkinsfile index 16e932e..11a9fa6 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -55,7 +55,7 @@ pipeline { }, "9.1-functest": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON,P100,TITANV -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p [email protected]:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -75,7 +75,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX,TITANX-L1ON,P100,TITANV $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX,TITANX-L1ON $PLOTDIR ${BUILD_NUMBER}' } } } diff --git a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config index f78bd02..28912a3 100644 --- a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config @@ -25,6 +25,7 @@ # shader core pipeline config -gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 61 # This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 4c0586d..8e93723 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -65,9 +65,9 @@ # Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB # Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:48:128:4,L:L:s:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index a70b077..e708fa7 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -665,6 +665,7 @@ enum cache_operator_type { CACHE_ALL, // .ca CACHE_LAST_USE, // .lu CACHE_VOLATILE, // .cv + CACHE_L1, // .nc // loads and stores CACHE_STREAMING, // .cs diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 9246613..93bbc1d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -898,6 +898,7 @@ void ptx_instruction::pre_decode() switch( m_cache_option ) { case CA_OPTION: cache_op = CACHE_ALL; break; + case NC_OPTION: cache_op = CACHE_L1; break; case CG_OPTION: cache_op = CACHE_GLOBAL; break; case CS_OPTION: cache_op = CACHE_STREAMING; break; case LU_OPTION: cache_op = CACHE_LAST_USE; break; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index ee36957..ba6d7ed 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1211,6 +1211,7 @@ ptx_instruction::ptx_instruction( int opcode, case EXTP_OPTION: break; case NC_OPTION: + m_cache_option = last_ptx_inst_option; break; case UP_OPTION: case DOWN_OPTION: diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 51689e3..0e2e1c2 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1642,7 +1642,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea bypassL1D = true; } else if (inst.space.is_global()) { // global memory access // skip L1 cache if the option is enabled - if (m_core->get_config()->gmem_skip_L1D) + if (m_core->get_config()->gmem_skip_L1D && (CACHE_L1 != inst.cache_op)) bypassL1D = true; } |