summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--configs/3.x-cfgs/GTX480/config_fermi_islip.icnt (renamed from configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt)2
-rw-r--r--configs/3.x-cfgs/GTX480/gpgpusim.config133
-rwxr-xr-xconfigs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml538
-rw-r--r--configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt (renamed from configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt)0
-rw-r--r--configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config (renamed from configs/4.x-cfgs/SM5_GTX750/gpgpusim.config)17
-rwxr-xr-xconfigs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml (renamed from configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml)0
-rw-r--r--configs/3.x-cfgs/QuadroFX5600/gpgpusim.config (renamed from configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config)13
-rw-r--r--configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml (renamed from configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml)0
-rw-r--r--configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt (renamed from configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt)0
-rw-r--r--configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt (renamed from configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt)0
-rw-r--r--configs/3.x-cfgs/QuadroFX5800/gpgpusim.config (renamed from configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config)13
-rw-r--r--configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt (renamed from configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt)0
-rw-r--r--configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config (renamed from configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config)0
-rwxr-xr-xconfigs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml (renamed from configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml)0
-rw-r--r--configs/3.x-cfgs/SM7_TITANV/gpgpusim.config165
-rw-r--r--configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt (renamed from configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt)0
-rw-r--r--configs/3.x-cfgs/TeslaC2050/gpgpusim.config (renamed from configs/4.x-cfgs/SM2_C2050/gpgpusim.config)15
-rw-r--r--configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt4
-rw-r--r--configs/4.x-cfgs/SM2_GTX480/gpgpusim.config23
-rw-r--r--configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt (renamed from configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt)1
-rw-r--r--configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config (renamed from configs/4.x-cfgs/SM7_TITANV/gpgpusim.config)70
-rw-r--r--src/gpgpu-sim/addrdec.cc17
-rw-r--r--src/gpgpu-sim/dram.cc12
-rw-r--r--src/gpgpu-sim/dram_sched.cc6
-rw-r--r--src/gpgpu-sim/gpu-sim.cc3
-rw-r--r--src/gpgpu-sim/shader.cc4
26 files changed, 779 insertions, 257 deletions
diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
index fac792a..7820e4e 100644
--- a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
// Topology
topology = fly;
-k = 64;
+k = 27;
n = 1;
// Routing
diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config
new file mode 100644
index 0000000..436cb41
--- /dev/null
+++ b/configs/3.x-cfgs/GTX480/gpgpusim.config
@@ -0,0 +1,133 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 20
+
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 15
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 6
+-gpgpu_n_sub_partition_per_mchannel 2
+
+# Fermi clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
+# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+-gpgpu_clock_domains 700.0:700.0:700.0:924.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+
+# This implies a maximum of 48 warps/SM
+-gpgpu_shader_core_pipeline 1536:32
+-gpgpu_shader_cta 8
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,1,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,16,8,8,130
+
+
+# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_shmem_size 49152
+
+# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
+#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_shmem_size 16384
+
+# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2_texture_only 0
+
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 6
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_num_reg_banks 16
+
+# shared memory bankconflict detection
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles). I.e.
+# Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_dram_return_queue_size 116
+
+# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4 # GDDR5 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS
+
+# GDDR5 timing from hynix H5GQ1H24AFR
+# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+ CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
diff --git a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
new file mode 100755
index 0000000..304e0fd
--- /dev/null
+++ b/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
@@ -0,0 +1,538 @@
+<?xml version="1.0" ?>
+<component id="root" name="root">
+ <component id="system" name="system">
+ <!--McPAT will skip the components if number is set to 0 -->
+ <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
+ <param name="number_of_cores" value="16"/>
+ <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
+ <param name="number_of_L1Directories" value="0"/>
+ <param name="number_of_L2Directories" value="0"/>
+ <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
+ <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
+ <param name="number_of_NoCs" value="1"/>
+ <param name="homogeneous_cores" value="1"/><!--1 means homo -->
+ <param name="homogeneous_L2s" value="1"/>
+ <param name="homogeneous_L1Directorys" value="1"/>
+ <param name="homogeneous_L2Directorys" value="1"/>
+ <param name="homogeneous_L3s" value="1"/>
+ <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
+ <param name="homogeneous_NoCs" value="1"/>
+ <param name="core_tech_node" value="40"/><!-- nm -->
+ <param name="target_core_clockrate" value="700"/><!--MHz -->
+ <param name="temperature" value="380"/> <!-- Kelvin -->
+ <param name="number_cache_levels" value="2"/>
+ <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
+ <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) -->
+ <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
+ <param name="machine_bits" value="32"/>
+ <param name="virtual_address_width" value="32"/>
+ <param name="physical_address_width" value="32"/>
+ <param name="virtual_memory_page_size" value="4096"/>
+ <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
+ <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
+ <param name="TOT_INST" value="2.00" />
+ <param name="FP_INT" value="4.57" />
+ <param name="IC_H" value="2.14" />
+ <param name="IC_M" value="22.47" />
+ <param name="DC_RH" value="22.14" />
+ <param name="DC_RM" value="24.66" />
+ <param name="DC_WH" value="1.53" />
+ <param name="DC_WM" value="39.79" />
+ <param name="TC_H" value="10.21" />
+ <param name="TC_M" value="24.66" />
+ <param name="CC_H" value="11.07" />
+ <param name="CC_M" value="12.33" />
+ <param name="SHRD_ACC" value="7.04" />
+ <param name="REG_RD" value="0.14" />
+ <param name="REG_WR" value="0.21" />
+ <param name="NON_REG_OPs" value="2.11" />
+ <param name="SP_ACC" value="2.38" />
+ <param name="SFU_ACC" value="0.51" />
+ <param name="FPU_ACC" value="0.64" />
+ <param name="MEM_RD" value="0.33" />
+ <param name="MEM_WR" value="0.40" />
+ <param name="MEM_PRE" value="0.11" />
+ <param name="L2_RH" value="13.79" />
+ <param name="L2_RM" value="35.18" />
+ <param name="L2_WH" value="43.07" />
+ <param name="L2_WM" value="28.72" />
+ <param name="NOC_A" value="305.48" />
+ <param name="PIPE_A" value="2.57" />
+ <param name="IDLE_CORE_N" value="1"/>
+ <param name="CONST_DYNAMICN" value="11" />
+ <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
+ <stat name="total_cycles" value="total_cycles_match_mcpat"/>
+ <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+ <stat name="busy_cycles" value="busy_cycles_match_mcpat"/>
+ <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of
+ virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank -->
+ <!-- *********************** cores ******************* -->
+ <component id="system.core0" name="core0">
+ <!-- Core property -->
+ <param name="clock_rate" value="700"/>
+ <param name="instruction_length" value="32"/>
+ <param name="opcode_width" value="9"/>
+ <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller
+ default value is machine_bits, if not set -->
+ <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
+ <!-- inorder/OoO -->
+ <param name="number_hardware_threads" value="32"/>
+ <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
+ it only may be more than one in SMT processors. BTB ports always equals to fetch ports since
+ branch information in consective branch instructions in the same fetch group can be read out from BTB once.-->
+ <param name="fetch_width" value="1"/>
+ <!-- fetch_width determins the size of cachelines of L1 cache block -->
+ <param name="number_instruction_fetch_ports" value="1"/>
+ <param name="decode_width" value="1"/>
+ <!-- decode_width determins the number of ports of the
+ renaming table (both RAM and CAM) scheme -->
+ <param name="issue_width" value="2"/>
+ <!-- issue_width determins the number of ports of Issue window and other logic
+ as in the complexity effective proccessors paper; issue_width==dispatch_width -->
+ <param name="commit_width" value="2"/>
+ <!-- commit_width determins the number of ports of register files -->
+ <param name="fp_issue_width" value="1"/>
+ <param name="prediction_width" value="0"/>
+ <!-- number of branch instructions can be predicted simultannouesl-->
+ <!-- Current version of McPAT does not distinguish int and floating point pipelines
+ Theses parameters are reserved for future use.-->
+ <param name="pipelines_per_core" value="1,1"/>
+ <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
+ <param name="pipeline_depth" value="8,8"/>
+ <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
+ <!-- issue and exe unit-->
+ <param name="ALU_per_core" value="32"/>
+ <!-- contains an adder, a shifter, and a logical unit -->
+ <param name="MUL_per_core" value="4"/>
+ <!-- For MUL and Div -->
+ <param name="FPU_per_core" value="32"/>
+ <!-- buffer between IF and ID stage -->
+ <param name="instruction_buffer_size" value="1"/>
+ <!-- buffer between ID and sche/exe stage -->
+ <param name="decoded_stream_buffer_size" value="1"/>
+ <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
+ <!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
+ <param name="instruction_window_size" value="1"/>
+ <param name="fp_instruction_window_size" value="1"/>
+ <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
+ <param name="ROB_size" value="0"/>
+ <!-- each in-flight instruction has an entry in ROB -->
+ <!-- registers -->
+ <!-- SM parameters Added by Syed Gilani -->
+ <param name="rf_banks" value="32"/>
+ <param name="simd_width" value="32"/>
+ <param name="collector_units" value="32"/>
+ <param name="core_clock_ratio" value="2"/>
+ <param name="warp_size" value="32"/>
+
+ <param name="archi_Regs_IRF_size" value="32768"/>
+ <param name="archi_Regs_FRF_size" value="32"/>
+ <!-- if OoO processor, phy_reg number is needed for renaming logic,
+ renaming logic is for both integer and floating point insts. -->
+ <param name="phy_Regs_IRF_size" value="32"/>
+ <param name="phy_Regs_FRF_size" value="32"/>
+ <!-- rename logic -->
+ <param name="rename_scheme" value="0"/>
+ <!-- can be RAM based(0) or CAM based(1) rename scheme
+ RAM-based scheme will have free list, status table;
+ CAM-based scheme have the valid bit in the data field of the CAM
+ both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
+ Detailed RAT Implementation see TR -->
+ <param name="register_windows_size" value="0"/>
+ <!-- how many windows in the windowed register file, sun processors;
+ no register windowing is used when this number is 0 -->
+ <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
+ They will always try to exeute out-of-order though. -->
+ <param name="LSU_order" value="inorder"/>
+ <param name="store_buffer_size" value="32"/>
+ <!-- By default, in-order cores do not have load buffers -->
+ <param name="load_buffer_size" value="32"/>
+ <!-- number of ports refer to sustainable concurrent memory accesses -->
+ <param name="memory_ports" value="2"/>
+ <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
+ as well as the ports of Dcache which is connected to LSU -->
+ <!-- dual-pumped Dcache can be used to save the extra read/write ports -->
+ <param name="RAS_size" value="1"/>
+ <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check -->
+ <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
+ <stat name="total_instructions" value="total_instructions_match_mcpat"/>
+ <stat name="int_instructions" value="int_instruction_match_mcpat"/>
+ <stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
+ <stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
+ <stat name="branch_mispredictions" value="0"/>
+ <stat name="load_instructions" value="load_instruction_match_mcpat"/>
+ <stat name="store_instructions" value="store_instruction_match_mcpat"/>
+ <stat name="committed_instructions" value="total_instructions_match_mcpat"/>
+ <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
+ <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
+ <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
+ <!-- the following cycle stats are used for heterogeneouse cores only,
+ please ignore them if homogeneouse cores -->
+ <stat name="total_cycles" value="total_cycles_match_mcpat"/>
+ <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
+ <stat name="busy_cycles" value="busy_cycles_match_mcpat"/>
+ <!-- instruction buffer stats -->
+ <!-- ROB stats, both RS and Phy based OoOs have ROB
+ performance simulator should capture the difference on accesses,
+ otherwise, McPAT has to guess based on number of commited instructions. -->
+ <stat name="ROB_reads" value="263886"/>
+ <stat name="ROB_writes" value="263886"/>
+ <!-- RAT accesses -->
+ <stat name="rename_accesses" value="263886"/>
+ <stat name="fp_rename_accesses" value="263886"/>
+ <!-- decode and rename stage use this, should be total ic - nop -->
+ <!-- Inst window stats -->
+ <stat name="inst_window_reads" value="263886"/>
+ <stat name="inst_window_writes" value="263886"/>
+ <stat name="inst_window_wakeup_accesses" value="263886"/>
+ <stat name="fp_inst_window_reads" value="263886"/>
+ <stat name="fp_inst_window_writes" value="263886"/>
+ <stat name="fp_inst_window_wakeup_accesses" value="263886"/>
+ <!-- RF accesses -->
+ <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
+ <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
+ <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
+ <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
+
+ <!-- The following stat is for operand collector power - Added by Syed -->
+ <stat name="non_rf_operands" value="0"/>
+
+ <!-- accesses to the working reg -->
+ <stat name="function_calls" value="0"/>
+ <stat name="context_switches" value="0"/> <!--not used in the McPAT -->
+ <!-- Number of Windowes switches (number of function calls and returns)-->
+ <!-- Alu stats by default, the processor has one FPU that includes the divider and
+ multiplier. The fpu accesses should include accesses to multiplier and divider -->
+ <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>
+ <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
+ <stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
+ <stat name="cdb_alu_accesses" value="0"/>
+ <stat name="cdb_mul_accesses" value="0"/>
+ <stat name="cdb_fpu_accesses" value="0"/>
+ <!-- multiple cycle accesses should be counted multiple times,
+ otherwise, McPAT can use internal counter for different floating point instructions
+ to get final accesses. But that needs detailed info for floating point inst mix -->
+ <!-- currently the performance simulator should
+ make sure all the numbers are final numbers,
+ including the explicit read/write accesses,
+ and the implicite accesses such as replacements and etc.
+ Future versions of McPAT may be able to reason the implicite access
+ based on param and stats of last level cache
+ The same rule applies to all cache access stats too! -->
+ <!-- following is AF for max power computation.
+ Do not change them, unless you understand them-->
+ <stat name="IFU_duty_cycle" value="0.25"/>
+ <stat name="LSU_duty_cycle" value="0.25"/>
+ <stat name="MemManU_I_duty_cycle" value="1"/>
+ <stat name="MemManU_D_duty_cycle" value="0.25"/>
+ <stat name="ALU_duty_cycle" value="0.9"/>
+ <stat name="MUL_duty_cycle" value="0.5"/>
+ <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
+ <stat name="ALU_cdb_duty_cycle" value="0.9"/>
+ <stat name="MUL_cdb_duty_cycle" value="0.5"/>
+ <stat name="FPU_cdb_duty_cycle" value="15"/>
+ <component id="system.core0.predictor" name="PBT">
+ <!-- branch predictor; tournament predictor see Alpha implementation -->
+ <param name="local_predictor_size" value="10,3"/>
+ <param name="local_predictor_entries" value="1024"/>
+ <param name="global_predictor_entries" value="4096"/>
+ <param name="global_predictor_bits" value="2"/>
+ <param name="chooser_predictor_entries" value="4096"/>
+ <param name="chooser_predictor_bits" value="2"/>
+ <!-- These parameters can be combined like below in next version
+ <param name="load_predictor" value="10,3,1024"/>
+ <param name="global_predictor" value="4096,2"/>
+ <param name="predictor_chooser" value="4096,2"/>
+ -->
+ </component>
+ <component id="system.core0.itlb" name="itlb">
+ <param name="number_entries" value="1"/>
+ <stat name="total_accesses" value="0"/>
+ <stat name="total_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ <!-- there is no write requests to itlb although writes happen to itlb after miss,
+ which is actually a replacement -->
+ </component>
+ <component id="system.core0.icache" name="icache">
+ <!-- there is no write requests to itlb although writes happen to it after miss,
+ which is actually a replacement -->
+ <param name="icache_config" value="16384,32,4,1,1,3,8,0"/>
+ <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+ <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
+ <param name="buffer_sizes" value="16, 16, 16,0"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="total_instructions_match_mcpat"/>
+ <stat name="read_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <component id="system.core0.dtlb" name="dtlb">
+ <param name="number_entries" value="1"/>
+ <stat name="total_accesses" value="0"/>
+ <stat name="total_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <component id="system.core0.ccache" name="ccache">
+ <!-- all the buffer related are optional -->
+ <param name="ccache_config" value="16384,32,4,1,1,3,8,0"/>
+ <param name="buffer_sizes" value="16, 16, 16, 0"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
+ <stat name="write_accesses" value="0"/>
+ <stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
+ <stat name="write_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <component id="system.core0.tcache" name="tcache">
+ <!-- all the buffer related are optional -->
+ <param name="tcache_config" value="16384,32,4,1,1,3,8,0"/>
+ <param name="buffer_sizes" value="16, 16, 16, 0"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
+ <stat name="write_accesses" value="0"/>
+ <stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
+ <stat name="write_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <!--model the shared memory by mimicing dcache-->
+ <component id="system.core0.sharedmemory" name="sharedmemory">
+ <!-- all the buffer related are optional -->
+ <param name="sharedmemory_config" value="49152,16,1,16,1,3,16,0"/>
+ <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+ <param name="buffer_sizes" value="16, 16, 16, 16"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
+ <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
+ <stat name="read_misses" value="0"/>
+ <stat name="write_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <component id="system.core0.dcache" name="dcache">
+ <!-- all the buffer related are optional -->
+ <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
+ <param name="buffer_sizes" value="16, 16, 16, 0"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
+ <stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
+ <stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
+ <stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
+ <stat name="conflicts" value="0"/>
+ </component>
+ <component id="system.core0.BTB" name="BTB">
+ <!-- all the buffer related are optional -->
+ <param name="BTB_config" value="8192,4,2,1, 1,3"/>
+ <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+ </component>
+ </component>
+ <component id="system.L1Directory0" name="L1Directory0">
+ <param name="Directory_type" value="0"/>
+ <!--0 cam based shadowed tag. 1 directory cache -->
+ <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
+ <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+ <param name="buffer_sizes" value="8, 8, 8, 8"/>
+ <!-- all the buffer related are optional -->
+ <param name="clockrate" value="1400"/>
+ <param name="ports" value="1,1,1"/>
+ <!-- number of r, w, and rw search ports -->
+ <param name="device_type" value="0"/>
+ <!-- altough there are multiple access types,
+ Performance simulator needs to cast them into reads or writes
+ e.g. the invalidates can be considered as writes -->
+ <stat name="read_accesses" value="800000"/>
+ <stat name="write_accesses" value="27276"/>
+ <stat name="read_misses" value="1632"/>
+ <stat name="write_misses" value="183"/>
+ <stat name="conflicts" value="20"/>
+ <stat name="duty_cycle" value="0.45"/>
+ </component>
+ <component id="system.L2Directory0" name="L2Directory0">
+ <param name="Directory_type" value="1"/>
+ <!--0 cam based shadowed tag. 1 directory cache -->
+ <param name="Dir_config" value="1048576,16,16,1,2, 100"/>
+ <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
+ <param name="buffer_sizes" value="8, 8, 8, 8"/>
+ <!-- all the buffer related are optional -->
+ <param name="clockrate" value="1400"/>
+ <param name="ports" value="1,1,1"/>
+ <!-- number of r, w, and rw search ports -->
+ <param name="device_type" value="0"/>
+ <!-- altough there are multiple access types,
+ Performance simulator needs to cast them into reads or writes
+ e.g. the invalidates can be considered as writes -->
+ <stat name="read_accesses" value="0"/>
+ <stat name="write_accesses" value="0"/>
+ <stat name="read_misses" value="0"/>
+ <stat name="write_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ <stat name="duty_cycle" value="0.45"/>
+ </component>
+ <component id="system.L20" name="L20">
+ <!-- all the buffer related are optional -->
+ <param name="L2_config" value="131072,256,8,1, 4,23, 64, 1"/>
+ <!-- consider 4-way bank interleaving for Niagara 1 -->
+ <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+ <param name="buffer_sizes" value="16, 16, 16, 16"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <param name="clockrate" value="1400"/>
+ <param name="ports" value="1,1,1"/>
+ <!-- number of r, w, and rw ports -->
+ <param name="device_type" value="0"/>
+ <stat name="read_accesses" value="200000"/>
+ <stat name="write_accesses" value="0"/>
+ <stat name="read_misses" value="0"/>
+ <stat name="write_misses" value="0"/>
+ <stat name="conflicts" value="0"/>
+ <stat name="duty_cycle" value="0.5"/>
+ </component>
+
+<!--**********************************************************************-->
+<component id="system.L30" name="L30">
+ <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
+ <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
+ <param name="clockrate" value="3500"/>
+ <param name="ports" value="1,1,1"/>
+ <!-- number of r, w, and rw ports -->
+ <param name="device_type" value="0"/>
+ <param name="buffer_sizes" value="16, 16, 16, 16"/>
+ <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
+ <stat name="read_accesses" value="58824"/>
+ <stat name="write_accesses" value="27276"/>
+ <stat name="read_misses" value="1632"/>
+ <stat name="write_misses" value="183"/>
+ <stat name="conflicts" value="0"/>
+ <stat name="duty_cycle" value="0.35"/>
+ </component>
+
+
+<!--**********************************************************************-->
+ <component id="system.NoC0" name="noc0">
+ <param name="clockrate" value="700"/>
+ <param name="type" value="1"/>
+ <!-- 1 NoC, O bus -->
+ <param name="horizontal_nodes" value="2"/>
+ <param name="vertical_nodes" value="1"/>
+ <param name="has_global_link" value="0"/>
+ <!-- 1 has global link, 0 does not have global link -->
+ <param name="link_throughput" value="1"/><!--w.r.t clock -->
+ <param name="link_latency" value="1"/><!--w.r.t clock -->
+ <!-- througput >= latency -->
+ <!-- Router architecture -->
+ <param name="input_ports" value="6"/>
+ <param name="output_ports" value="6"/>
+ <param name="virtual_channel_per_port" value="1"/>
+ <!-- input buffer; in classic routers only input ports need buffers -->
+ <param name="flit_bits" value="32"/>
+ <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
+ <param name="chip_coverage" value="1"/>
+ <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
+ <stat name="total_accesses" value="0"/>
+ <!-- This is the number of total accesses within the whole network not for each router -->
+ <stat name="duty_cycle" value="0.6"/>
+ </component>
+<!--**********************************************************************-->
+<!--**********************************************************************-->
+
+ <component id="system.mem" name="mem">
+ <!-- Main memory property -->
+ <param name="mem_tech_node" value="40"/>
+ <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
+ <param name="peak_transfer_rate" value="3200"/><!--MB/S-->
+ <param name="internal_prefetch_of_DRAM_chip" value="4"/>
+ <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
+ <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
+ <!-- above numbers can be easily found from Wikipedia -->
+ <param name="capacity_per_channel" value="4096"/> <!-- MB -->
+ <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
+ Current McPAT assumes single DIMMs are used.-->
+ <param name="number_ranks" value="2"/>
+ <param name="num_banks_of_DRAM_chip" value="6"/>
+ <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
+ <param name="output_width_of_DRAM_chip" value="8"/>
+ <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+ <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
+ <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
+ <param name="burstlength_of_DRAM_chip" value="8"/>
+ <stat name="memory_accesses" value="1052"/>
+ <stat name="memory_reads" value="1052"/>
+ <stat name="memory_writes" value="1052"/>
+ </component>
+ <component id="system.mc" name="mc">
+ <!-- Memeory controllers are for DDR(2,3...) DIMMs -->
+ <!-- current version of McPAT uses published values for base parameters of memory controller
+ improvments on MC will be added in later versions. -->
+ <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+ <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1-->
+ <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
+ <param name="block_size" value="64"/><!--B-->
+ <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers -->
+ <!-- current McPAT only supports homogeneous memory controllers -->
+ <param name="memory_channels_per_mc" value="2"/>
+ <param name="number_ranks" value="1"/>
+ <param name="withPHY" value="0"/>
+ <!-- # of ranks of each channel-->
+ <param name="req_window_size_per_channel" value="16"/>
+ <param name="IO_buffer_size_per_channel" value="16"/>
+ <param name="databus_width" value="32"/>
+ <param name="addressbus_width" value="32"/>
+ <param name="PRT_entries" value="32"/>
+ <!-- # of empirical DRAM model parameter -->
+ <param name="dram_cmd_coeff" value="0"/>
+ <param name="dram_act_coeff" value="0"/>
+ <param name="dram_nop_coeff" value="0"/>
+ <param name="dram_activity_coeff" value="0"/>
+ <param name="dram_pre_coeff" value="3.8475e-8f"/>
+ <param name="dram_rd_coeff" value="7.74707143e-8f"/>
+ <param name="dram_wr_coeff" value="3.54664286e-8f"/>
+ <param name="dram_req_coeff" value="0"/>
+ <param name="dram_const_coeff" value="0"/>
+
+ <!-- McPAT will add the control bus width to the addressbus width automatically -->
+ <stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
+ <stat name="memory_reads" value="memory_reads_match_mcpat"/>
+ <stat name="memory_writes" value="memory_writes_match_mcpat"/>
+ <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate
+ the average power per MC or per channel. This is sufficent for most application.
+ Further trackdown can be easily added in later versions. -->
+ </component>
+<!--**********************************************************************-->
+ <component id="system.niu" name="niu">
+ <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller -->
+ <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns.
+ the low bound of clock rate of a 10Gb MAC is 150Mhz -->
+ <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+ <param name="clockrate" value="350"/>
+ <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
+ <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+ <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth -->
+ <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate
+ the average power per nic or per channel. This is sufficent for most application. -->
+ </component>
+<!--**********************************************************************-->
+ <component id="system.pcie" name="pcie">
+ <!-- On chip PCIe controller, including Phy-->
+ <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns.
+ the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
+ <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
+ <param name="withPHY" value="1"/>
+ <param name="clockrate" value="350"/>
+ <param name="number_units" value="0"/>
+ <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
+ <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+ <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth -->
+ <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate
+ the average power per pcie controller or per channel. This is sufficent for most application. -->
+ </component>
+<!--**********************************************************************-->
+ <component id="system.flashc" name="flashc">
+ <param name="number_flashcs" value="0"/>
+ <param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
+ <param name="withPHY" value="1"/>
+ <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
+ <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
+ <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth -->
+ <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate
+ the average power per fc or per channel. This is sufficent for most application -->
+ </component>
+<!--**********************************************************************-->
+
+ </component>
+</component>
diff --git a/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt b/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
index 069ca02..069ca02 100644
--- a/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
index 9366f93..8b030b6 100644
--- a/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -28,11 +28,10 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
-gpgpu_num_sp_units 8
-gpgpu_num_sfu_units 32
--gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -43,21 +42,21 @@
-ptx_opcode_latency_dp 8,19,8,8,330
-ptx_opcode_initiation_dp 8,16,8,8,130
--gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
-gmem_skip_L1D 1
-gpgpu_shmem_size 65536
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache
--gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
diff --git a/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml b/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
index e2b2324..e2b2324 100755
--- a/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
index e3cab18..cb87b65 100644
--- a/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config
+++ b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
@@ -17,11 +17,10 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
-gpgpu_num_sp_units 1
-gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -33,10 +32,10 @@
-ptx_opcode_initiation_dp 8,8,8,8,130
# memory stage behaviour
--gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
# TLB parameters
diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml b/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
index 2c5a6fc..2c5a6fc 100644
--- a/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml
+++ b/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
diff --git a/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt b/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
index de3bcc8..de3bcc8 100644
--- a/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt
+++ b/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
diff --git a/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt b/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
index cfe9cac..cfe9cac 100644
--- a/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt
+++ b/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
diff --git a/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
index 56dbb17..82243c2 100644
--- a/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config
+++ b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
@@ -16,11 +16,10 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+-gpgpu_pipeline_widths 1,1,1,1,1,1,1
-gpgpu_num_sp_units 1
-gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -34,10 +33,10 @@
# memory stage behaviour
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
--gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
-gpgpu_shmem_warp_parts 2
diff --git a/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
index 2a69ddd..2a69ddd 100644
--- a/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
+++ b/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
index 47c2b6a..47c2b6a 100644
--- a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config
+++ b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
index 02619ff..02619ff 100755
--- a/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
+++ b/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
deleted file mode 100644
index f1ae2dc..0000000
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ /dev/null
@@ -1,165 +0,0 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1#
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 40
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1
-
-# volta clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100 clock domains are adopted from
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32
--gpgpu_shader_cta 32
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,1,4,4,1,9
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0
--gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 1
--gpgpu_shmem_size_PrefShared 98304
--gmem_skip_L1D 0
-
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache
--gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
--gpgpu_dram_partition_queues 64:64:64:64
-
-# 128 KB Inst.
--gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
-# 48 KB Tex
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
-
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 14
--gpgpu_operand_collector_num_units_sfu 8
--gpgpu_operand_collector_num_units_mem 10
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 1
-
-# interconnection
--network_mode 1
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles). I.e.
-# Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2 # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
- CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt b/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
index a11bd8e..a11bd8e 100644
--- a/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt
+++ b/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM2_C2050/gpgpusim.config b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
index aa5f5f3..442ab8b 100644
--- a/configs/4.x-cfgs/SM2_C2050/gpgpusim.config
+++ b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
@@ -33,10 +33,9 @@
# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+-gpgpu_pipeline_widths 2,1,1,2,1,1,2
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 1
--gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -52,20 +51,20 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
-gpgpu_shmem_size 49152
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
index 7820e4e..d372b26 100644
--- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
@@ -1,6 +1,6 @@
//21*1 fly with 32 flits per packet under gpgpusim injection mode
use_map = 0;
-flit_size = 32;
+flit_size = 40;
// currently we do not use this, see subnets below
network_count = 2;
@@ -17,7 +17,7 @@ routing_function = dest_tag;
// Flow control
num_vcs = 1;
-vc_buf_size = 8;
+vc_buf_size = 64;
wait_for_tail_credit = 0;
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 03fcda1..7f8da49 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -50,20 +50,25 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:128:8,8
-gpgpu_shmem_size 49152
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,S:32:8,8
#-gpgpu_shmem_size 16384
# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 0
+-memory_partition_indexing 0
--gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
@@ -76,6 +81,7 @@
-gpgpu_shmem_num_banks 32
-gpgpu_shmem_limited_broadcast 0
-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 20
-gpgpu_max_insn_issue_per_warp 1
@@ -110,6 +116,13 @@
-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
# Fermi has two schedulers per core
-gpgpu_num_sched_per_core 2
# Two Level Scheduler with active and pending pools
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
index 616e9f3..81153b0 100644
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
@@ -14,7 +14,6 @@ n = 1;
routing_function = dest_tag;
-
// Flow control
num_vcs = 1;
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
index da98547..edcd919 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
@@ -1,35 +1,23 @@
-# This config models the Volta Titan X
-# For more info about this card:
-# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
-# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1#
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
-# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
-# https://devblogs.nvidia.com/inside-volta/
-# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
-
# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 70
+-gpgpu_ptx_force_max_capability 60
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
# high level architecture configuration
--gpgpu_n_clusters 40
+-gpgpu_n_clusters 32
-gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 24
+-gpgpu_n_mem 32
-gpgpu_n_sub_partition_per_mchannel 1
-# volta clock domains
+# Pscal clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
# Pascal NVIDIA GP100 clock domains are adopted from
-# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
-# boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# https://en.wikipedia.org/wiki/Nvidia_Tesla
+-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
# shader core pipeline config
-gpgpu_shader_registers 65536
@@ -43,52 +31,52 @@
# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
--gpgpu_num_dp_units 4
+-gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 2
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from
-# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
-ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_initiation_int 1,1,1,1,4
-ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 4,4,4,4,130
--ptx_opcode_latency_sfu 100
--ptx_opcode_initiation_sfu 8
+-ptx_opcode_initiation_dp 2,2,2,2,130
+-ptx_opcode_latency_sfu 8
+-ptx_opcode_initiation_sfu 4
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
-gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 1
--gpgpu_shmem_size_PrefShared 98304
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
-gmem_skip_L1D 0
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:256:4,32:0,32
+# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 64:64:64:64
-perf_sim_memcpy 0
+-memory_partition_indexing 2
-# 128 KB Inst.
--gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
# 48 KB Tex
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 64 KB Const
--gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 12
@@ -112,7 +100,7 @@
-gpgpu_coalesce_arch 60
## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 1
+-gpgpu_max_insn_issue_per_warp 2
-gpgpu_dual_issue_diff_exec_units 1
# interconnection
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index cfd90ec..e7e27b7 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -132,7 +132,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0];
chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1];
chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2];
- chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3];
+ chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3];
chip[4] = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^chip[4];
tlx->chip = chip.to_ulong();
@@ -144,8 +144,21 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
assert(tlx->chip < m_n_channel);
break;
case CUSTOM:
- /* No custom set function implemented */
+ {
+ //random selected bits
+ //do you custom hashing function here, similar to
+ //Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018
+ std::bitset<64> b(tlx->row);
+ std::bitset<5> chip(tlx->chip);
+ chip[0] = b[13]^b[10]^b[9]^b[5]^b[0]^chip[0];
+ chip[1] = b[12]^b[11]^b[6]^b[1]^chip[1];
+ chip[2] = b[14]^b[9]^b[8]^b[7]^b[2]^chip[2];
+ chip[3] = b[11]^b[10]^b[8]^b[3]^chip[3];
+ chip[4] = b[12]^b[9]^b[8]^b[5]^b[4]^chip[4];
+ tlx->chip = chip.to_ulong();
+ assert(tlx->chip < m_n_channel);
break;
+ }
default:
assert("\nUndefined set index function.\n" && 0);
break;
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 92aa819..ac63327 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -730,13 +730,15 @@ void dram_t::print( FILE* simFile) const
printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total);
printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total);
- printf("\nbwutil = %.6f \n", (float)bwutil/n_cmd);
+ printf("\nBW Util details:\n");
+ printf("bwutil = %.6f \n", (float)bwutil/n_cmd);
printf("total_CMD = %d \n", n_cmd);
printf("util_bw = %d \n", util_bw);
printf("Wasted_Col = %d \n", wasted_bw_col);
- printf("Wasted_Row %d \n", wasted_bw_row);
- printf("Idle = %d \n\n", idle_bw);
+ printf("Wasted_Row = %d \n", wasted_bw_row);
+ printf("Idle = %d \n", idle_bw);
+ printf("\nBW Util Bottlenecks: \n");
printf("RCDc_limit = %d \n", RCDc_limit);
printf("RCDWRc_limit = %d \n", RCDWRc_limit);
printf("WTRc_limit = %d \n", WTRc_limit);
@@ -747,6 +749,7 @@ void dram_t::print( FILE* simFile) const
printf("WTRc_limit_alone = %d \n", WTRc_limit_alone);
printf("RTWc_limit_alone = %d \n", RTWc_limit_alone);
+ printf("\nCommands details: \n");
printf("total_CMD = %d \n", n_cmd);
printf("n_nop = %d \n", n_nop);
printf("Read = %d \n", n_rd);
@@ -757,8 +760,9 @@ void dram_t::print( FILE* simFile) const
printf("n_pre = %d \n", n_pre);
printf("n_ref = %d \n", n_ref);
printf("n_req = %d \n", n_req );
- printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
+ printf("total_req = %d \n", n_rd+n_wr+n_rd_L2_A+n_wr_WB);
+ printf("\nDual Bus Interface Util: \n");
printf("issued_total_row = %lu \n", issued_total_row);
printf("issued_total_col = %lu \n", issued_total_col);
printf("Row_Bus_Util = %.6f \n", (float)issued_total_row / n_cmd);
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index f754d36..ff50050 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -109,12 +109,14 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row )
if(m_config->seperate_write_queue_enabled) {
if(m_mode == READ_MODE &&
((m_num_write_pending >= m_config->write_high_watermark )
- || (m_queue[bank].empty() && !m_write_queue[bank].empty()))) {
+ // || (m_queue[bank].empty() && !m_write_queue[bank].empty())
+ )) {
m_mode = WRITE_MODE;
}
else if(m_mode == WRITE_MODE &&
(( m_num_write_pending < m_config->write_low_watermark )
- || (!m_queue[bank].empty() && m_write_queue[bank].empty()))){
+ // || (!m_queue[bank].empty() && m_write_queue[bank].empty())
+ )){
m_mode = READ_MODE;
}
}
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d48de25..ea2dfba 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1495,7 +1495,8 @@ void gpgpu_sim::cycle()
} else {
mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
- partiton_reqs_in_parallel_per_cycle++;
+ if(mf)
+ partiton_reqs_in_parallel_per_cycle++;
}
m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4828875..b59e5d2 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -451,7 +451,7 @@ void shader_core_stats::print( FILE* fout ) const
fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge);
fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict);
- fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
+ fprintf(fout, "gpgpu_stall_shd_mem[c_mem][resource_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
//fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]);
//fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]);
//fprintf(fout, "gpgpu_stall_shd_mem[c_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][DATA_PORT_STALL]);
@@ -459,7 +459,7 @@ void shader_core_stats::print( FILE* fout ) const
//fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]);
//fprintf(fout, "gpgpu_stall_shd_mem[t_mem][data_port_stall] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][DATA_PORT_STALL]);
fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]);
- fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n",
+ fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][resource_stall] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] +
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 00:30:00 +0000