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-rw-r--r--CHANGES14
-rw-r--r--configs/GTX480/gpgpusim.config15
-rw-r--r--configs/QuadroFX5600/gpgpusim.config8
-rw-r--r--configs/QuadroFX5800/gpgpusim.config10
-rw-r--r--configs/TeslaC2050/gpgpusim.config15
-rw-r--r--src/gpgpu-sim/gpu-cache.cc49
-rw-r--r--src/gpgpu-sim/gpu-cache.h48
-rw-r--r--src/gpgpu-sim/shader.h2
8 files changed, 122 insertions, 39 deletions
diff --git a/CHANGES b/CHANGES
index 28a3766..c994737 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,11 +1,17 @@
LOG:
Version 3.2.3+edits (development branch) versus 3.2.3
-- Fixed bug #81, fix ordering of pushing branch entries to the stack
+- Added a parameter to the cache configuration to configure the set index
+ function. Added a hash set index function to the Fermi L1 data cache for
+ the two default cache sizes, 16KB/48KB with 32/64 sets.
+
+- Bug fixes:
+ - Fixed bug #81, fix ordering of pushing branch entries to the stack
Version 3.2.3 versus 3.2.2
-- Fixed bug #78, added signed types to implementation of slct instruction.
-- Fixed bug #64, properly handing unsigned add.
-- Fixed bug #80, sad instruction operands were not corret.
+- Bug fixes:
+ - Fixed bug #78, added signed types to implementation of slct instruction.
+ - Fixed bug #64, properly handing unsigned add.
+ - Fixed bug #80, sad instruction operands were not corret.
Version 3.2.2 versus 3.2.1
- Added NVIDIA Quadro FX5600 GPGPU-Sim and GPUWattch configuration files.
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index b0035a5..436cb41 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -45,22 +45,23 @@
# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:dl1 32:128:4,L:L:m:N,A:32:8,8
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
-gpgpu_shmem_size 49152
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 64:128:6,L:L:m:N,A:32:8,8
+#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W,A:32:4,4:0,32
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config
index 775a31a..cb87b65 100644
--- a/configs/QuadroFX5600/gpgpusim.config
+++ b/configs/QuadroFX5600/gpgpusim.config
@@ -32,10 +32,10 @@
-ptx_opcode_initiation_dp 8,8,8,8,130
# memory stage behaviour
--gpgpu_cache:il1 4:256:4,L:R:f:N,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W,A:16:4,4
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
# TLB parameters
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 0df4b64..82243c2 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -31,12 +31,12 @@
-ptx_opcode_initiation_dp 8,8,8,8,130
# memory stage behaviour
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:il1 4:256:4,L:R:f:N,A:2:32,4
--gpgpu_tex_cache:l1 8:128:5,L:R:m:N,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
--gpgpu_cache:dl2 16:256:8,L:B:m:W,A:16:4,4
+-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
-gpgpu_shmem_warp_parts 2
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 416b171..442ab8b 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -48,22 +48,23 @@
# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
--gpgpu_cache:dl1 32:128:4,L:L:m:N,A:32:8,8
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
-gpgpu_shmem_size 49152
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 64:128:6,L:L:m:N,A:32:8,8
+#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W,A:32:4,4:0,32
+-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 4:128:4,L:R:f:N,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4
+-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 2137d2e..5ea4190 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -47,6 +47,55 @@ const char * cache_request_status_str(enum cache_request_status status)
return static_cache_request_status_str[status];
}
+unsigned l1d_cache_config::set_index(new_addr_type addr) const{
+ unsigned set_index = m_nset; // Default to linear set index function
+ unsigned lower_xor = 0;
+ unsigned upper_xor = 0;
+
+ switch(m_set_index_function){
+ case FERMI_HASH_SET_FUNCTION:
+ /*
+ * Set Indexing function from "A Detailed GPU Cache Model Based on Reuse Distance Theory"
+ * Cedric Nugteren et al.
+ * ISCA 2014
+ */
+ if(m_nset == 32 || m_nset == 64){
+ // Lower xor value is bits 7-11
+ lower_xor = (addr >> m_line_sz_log2) & 0x1F;
+
+ // Upper xor value is bits 13, 14, 15, 17, and 19
+ upper_xor = (addr & 0xE000) >> 13; // Bits 13, 14, 15
+ upper_xor |= (addr & 0x20000) >> 14; // Bit 17
+ upper_xor |= (addr & 0x80000) >> 15; // Bit 19
+
+ set_index = (lower_xor ^ upper_xor);
+
+ // 48KB cache prepends the set_index with bit 12
+ if(m_nset == 64)
+ set_index |= (addr & 0x1000) >> 7;
+
+ }else{ /* Else incorrect number of sets for the hashing function */
+ assert("\nGPGPU-Sim cache configuration error: The number of sets should be "
+ "32 or 64 for the hashing set index function.\n" && 0);
+ }
+ break;
+
+ case CUSTOM_SET_FUNCTION:
+ /* No custom set function implemented */
+ break;
+
+ case LINEAR_SET_FUNCTION:
+ set_index = (addr >> m_line_sz_log2) & (m_nset-1);
+ break;
+ }
+
+ // Linear function selected or custom set index function not implemented
+ assert((set_index < m_nset) && "\nError: Set index out of bounds. This is caused by "
+ "an incorrect or unimplemented custom set index function.\n");
+
+ return set_index;
+}
+
void l2_cache_config::init(linear_to_raw_address_translation *address_mapping){
cache_config::init(m_config_string,FuncCachePreferNone);
m_address_mapping = address_mapping;
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index a775ac9..7535a1d 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -123,6 +123,11 @@ enum mshr_config_t {
ASSOC // normal cache
};
+enum set_index_function{
+ FERMI_HASH_SET_FUNCTION = 0,
+ LINEAR_SET_FUNCTION,
+ CUSTOM_SET_FUNCTION
+};
class cache_config {
public:
@@ -133,18 +138,20 @@ public:
m_config_string = NULL; // set by option parser
m_config_stringPrefL1 = NULL;
m_config_stringPrefShared = NULL;
- m_data_port_width = 0;
+ m_data_port_width = 0;
+ m_set_index_function = LINEAR_SET_FUNCTION;
}
void init(char * config, FuncCache status)
{
cache_status= status;
assert( config );
- char rp, wp, ap, mshr_type, wap;
+ char rp, wp, ap, mshr_type, wap, sif;
+
- int ntok = sscanf(config,"%u:%u:%u,%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
+ int ntok = sscanf(config,"%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
&m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap,
- &mshr_type, &m_mshr_entries,&m_mshr_max_merge,
- &m_miss_queue_size,&m_result_fifo_entries,
+ &sif,&mshr_type,&m_mshr_entries,&m_mshr_max_merge,
+ &m_miss_queue_size, &m_result_fifo_entries,
&m_data_port_width);
if ( ntok < 11 ) {
@@ -173,7 +180,7 @@ public:
default: exit_parse_error();
}
switch (mshr_type) {
- case 'F': m_mshr_type = TEX_FIFO; assert(ntok==12); break;
+ case 'F': m_mshr_type = TEX_FIFO; assert(ntok==13); break;
case 'A': m_mshr_type = ASSOC; break;
default: exit_parse_error();
}
@@ -206,6 +213,13 @@ public:
m_data_port_width = m_line_sz;
}
assert(m_line_sz % m_data_port_width == 0);
+
+ switch(sif){
+ case 'H': m_set_index_function = FERMI_HASH_SET_FUNCTION; break;
+ case 'C': m_set_index_function = CUSTOM_SET_FUNCTION; break;
+ case 'L': m_set_index_function = LINEAR_SET_FUNCTION; break;
+ default: exit_parse_error();
+ }
}
bool disabled() const { return m_disabled;}
unsigned get_line_sz() const
@@ -228,17 +242,24 @@ public:
virtual unsigned set_index( new_addr_type addr ) const
{
+ if(m_set_index_function != LINEAR_SET_FUNCTION){
+ printf("\nGPGPU-Sim cache configuration error: Hashing or "
+ "custom set index function selected in configuration "
+ "file for a cache that has not overloaded the set_index "
+ "function\n");
+ abort();
+ }
return(addr >> m_line_sz_log2) & (m_nset-1);
}
new_addr_type tag( new_addr_type addr ) const
{
- // For generality, the tag includes both index and tag. This allows for more complex set index
- // calculations that can result in different indexes mapping to the same set, thus the full
- // tag + index is required to check for hit/miss. Tag is now identical to the block address.
+ // For generality, the tag includes both index and tag. This allows for more complex set index
+ // calculations that can result in different indexes mapping to the same set, thus the full
+ // tag + index is required to check for hit/miss. Tag is now identical to the block address.
//return addr >> (m_line_sz_log2+m_nset_log2);
- return addr & ~(m_line_sz-1);
+ return addr & ~(m_line_sz-1);
}
new_addr_type block_addr( new_addr_type addr ) const
{
@@ -285,8 +306,8 @@ protected:
unsigned m_rob_entries;
};
unsigned m_result_fifo_entries;
-
unsigned m_data_port_width; //< number of byte the cache can access per cycle
+ enum set_index_function m_set_index_function; // Hash, linear, or custom set index function
friend class tag_array;
friend class baseline_cache;
@@ -297,6 +318,11 @@ protected:
friend class l2_cache;
};
+class l1d_cache_config : public cache_config{
+public:
+ l1d_cache_config() : cache_config(){}
+ virtual unsigned set_index(new_addr_type addr) const;
+};
class l2_cache_config : public cache_config {
public:
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 6f31523..78ac55e 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1274,7 +1274,7 @@ struct shader_core_config : public core_config
mutable cache_config m_L1I_config;
mutable cache_config m_L1T_config;
mutable cache_config m_L1C_config;
- mutable cache_config m_L1D_config;
+ mutable l1d_cache_config m_L1D_config;
bool gmem_skip_L1D; // on = global memory access always skip the L1 cache
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 22:26:31 +0000