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-rw-r--r--src/cuda-sim/cuda-sim.cc21
-rw-r--r--src/gpgpu-sim/gpu-sim.cc5
-rw-r--r--src/gpgpu-sim/shader.h23
3 files changed, 27 insertions, 22 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 7587db7..86a1d45 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -69,9 +69,9 @@ unsigned cdp_latency[5];
void ptx_opcocde_latency_options (option_parser_t opp) {
option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
- "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>"
- "Default 1,1,19,25,145,1,4",
- "1,1,19,25,145,1,4");
+ "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>"
+ "Default 1,1,19,25,145",
+ "1,1,19,25,145");
option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp,
"Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,1,1,30",
@@ -81,9 +81,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
"Default 8,8,8,8,335",
"8,8,8,8,335");
option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
- "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>"
- "Default 1,1,4,4,32,1,1",
- "1,1,4,4,32,1");
+ "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
+ "Default 1,1,4,4,32",
+ "1,1,4,4,32");
option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp,
"Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,1,1,5",
@@ -590,13 +590,9 @@ void ptx_instruction::set_bar_type()
void ptx_instruction::set_opcode_and_latency()
{
unsigned int_latency[5];
- unsigned int_precision;
- unsigned int_lane_width;
unsigned fp_latency[5];
unsigned dp_latency[5];
unsigned int_init[5];
- unsigned int_init_precision;
- unsigned int_init_lane_width;
unsigned fp_init[5];
unsigned dp_init[5];
/*
@@ -605,11 +601,10 @@ void ptx_instruction::set_opcode_and_latency()
* [2] MUL
* [3] MAD
* [4] DIV
- * [5] BSMAD
*/
sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u",
&int_latency[0],&int_latency[1],&int_latency[2],
- &int_latency[3],&int_latency[4],&int_precision,&int_lane_width);
+ &int_latency[3],&int_latency[4]);
sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
&fp_latency[0],&fp_latency[1],&fp_latency[2],
&fp_latency[3],&fp_latency[4]);
@@ -618,7 +613,7 @@ void ptx_instruction::set_opcode_and_latency()
&dp_latency[3],&dp_latency[4]);
sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u",
&int_init[0],&int_init[1],&int_init[2],
- &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width);
+ &int_init[3],&int_init[4]);
sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u",
&fp_init[0],&fp_init[1],&fp_init[2],
&fp_init[3],&fp_init[4]);
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d4b636b..63ba759 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -369,8 +369,11 @@ void shader_core_config::reg_options(class OptionParser * opp)
"1");
option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
"Pipeline widths "
- "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
+ "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
"1,1,1,1,1,1,1,1,1,1" );
+ option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32, &gpgpu_tensor_core_avail,
+ "Tensor Core Available (default=0)",
+ "0");
option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units,
"Number of SP units (default=1)",
"1");
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 8ad6514..97e438f 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1228,26 +1228,26 @@ protected:
enum pipeline_stage_name_t {
ID_OC_SP=0,
ID_OC_SFU,
- ID_OC_TENSOR_CORE,
ID_OC_MEM,
OC_EX_SP,
OC_EX_SFU,
- OC_EX_TENSOR_CORE,
OC_EX_MEM,
EX_WB,
+ ID_OC_TENSOR_CORE,
+ OC_EX_TENSOR_CORE,
N_PIPELINE_STAGES
};
const char* const pipeline_stage_name_decode[] = {
"ID_OC_SP",
"ID_OC_SFU",
- "ID_OC_TENSOR_CORE",
"ID_OC_MEM",
"OC_EX_SP",
"OC_EX_SFU",
- "OC_EX_TENSOR_CORE",
"OC_EX_MEM",
"EX_WB",
+ "ID_OC_TENSOR_CORE",
+ "OC_EX_TENSOR_CORE",
"N_PIPELINE_STAGES"
};
@@ -1272,16 +1272,22 @@ struct shader_core_config : public core_config
strcpy(toks,pipeline_widths_string);
toks = strtok(toks,",");
- // pipe_widths[OC_EX_TENSOR_CORE]=1;
- // pipe_widths[ID_OC_TENSOR_CORE]=1;
- for (unsigned i = 0; i < N_PIPELINE_STAGES; i++) {
+
+ /* Removing the tensorcore pipeline while reading the config files if the tensor core is not available.
+ If we won't remove it, old regression will be broken.
+ So to support the legacy config files it's best to handle in this way.
+ */
+ int num_config_to_read=N_PIPELINE_STAGES-2*(!gpgpu_tensor_core_avail);
+
+ for (unsigned i = 0; i <num_config_to_read; i++) {
assert(toks);
ntok = sscanf(toks,"%d", &pipe_widths[i]);
assert(ntok == 1);
toks = strtok(NULL,",");
}
- delete[] tokd;
+ delete[] tokd;
+
if (n_thread_per_shader > MAX_THREAD_PER_SM) {
printf("GPGPU-Sim uArch: Error ** increase MAX_THREAD_PER_SM in abstract_hardware_model.h from %u to %u\n",
MAX_THREAD_PER_SM, n_thread_per_shader);
@@ -1361,6 +1367,7 @@ struct shader_core_config : public core_config
unsigned int gpgpu_operand_collector_num_out_ports_gen;
int gpgpu_num_sp_units;
+ int gpgpu_tensor_core_avail;
int gpgpu_num_sfu_units;
int gpgpu_num_tensor_core_units;
int gpgpu_num_mem_units;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:26:29 +0000