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-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt73
-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config186
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config34
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config192
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config3
-rw-r--r--configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt73
-rw-r--r--configs/tested-cfgs/Turing_RTX2060/gpgpusim.config186
-rw-r--r--src/gpgpu-sim/gpu-sim.cc3
-rw-r--r--src/gpgpu-sim/gpu-sim.h4
-rw-r--r--src/trace-driven/gpgpusim_trace_driven_main.cc6
-rw-r--r--src/trace-driven/kepler_opcode.h141
-rw-r--r--src/trace-driven/pascal_opcode.h8
-rw-r--r--src/trace-driven/trace_driven.cc5
-rw-r--r--src/trace-driven/trace_opcode.h7
15 files changed, 899 insertions, 24 deletions
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt
new file mode 100644
index 0000000..2fe3b53
--- /dev/null
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/config_kepler_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40;
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 38;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters = 1;
+
+credit_delay = 0;
+routing_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup = 1;
+output_speedup = 1;
+internal_speedup = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
new file mode 100644
index 0000000..323d2d9
--- /dev/null
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -0,0 +1,186 @@
+# This config models the KEPLER (TITAN)
+# For more info about this card, see Nvidia White paper
+# https://wr0.wr.inf.h-brs.de/wr/hardware/nodes3/nvidia/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 35
+-gpgpu_ignore_resources_limitation 1
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
+# Compute Capability
+-gpgpu_compute_capability_major 3
+-gpgpu_compute_capability_minor 5
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster
+-gpgpu_n_clusters 14
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2
+
+# Kepler clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Kepler NVIDIA TITAN clock domains are adopted from
+# https://en.wikipedia.org/wiki/GeForce_700_series
+-gpgpu_clock_domains 837.0:837.0:837.0:1502.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 62
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 2048:32
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Kepler has 6 SP SIMD units and 2 SFU units per SM.
+# There is no int unit in kepler
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 6,4,0,2,1,6,4,0,2,1,12
+-gpgpu_num_sp_units 6
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 4
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 2,8,8,8,130
+-ptx_opcode_initiation_sfu 2
+-ptx_opcode_latency_sfu 200
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1 S:4:128:32,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:4:128:32,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_sizeDefault 49152
+-gpgpu_shmem_size_PrefL1 16384
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Kepler P102 and only enabled for local memory
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 1.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use kepler Coalsce arhitetecture
+-gpgpu_coalesce_arch 35
+
+## In Kepler, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 0
+
+# interconnection
+-network_mode 1
+-inter_config_file config_kepler_islip.icnt
+
+# memory partition latency config
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 64
+
+# for NVIDIA TITAN, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4 # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing, scaled to 2500MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+ CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Kepler TITAN has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Kepler
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index e6d8f1d..f8689c2 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -25,7 +25,7 @@
# high level architecture configuration
# P102 has two semi-indp scheds per core, and two cores per cluster
-gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
+-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 12
-gpgpu_n_sub_partition_per_mchannel 2
@@ -36,12 +36,12 @@
-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
# shader core pipeline config
--gpgpu_shader_registers 32768
+-gpgpu_shader_registers 65536
-gpgpu_occupancy_sm_number 62
# This implies a maximum of 32 warps/SM
--gpgpu_shader_core_pipeline 1024:32
--gpgpu_shader_cta 16
+-gpgpu_shader_core_pipeline 2048:32
+-gpgpu_shader_cta 32
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
@@ -49,9 +49,9 @@
## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
# There is no int unit in Pascal
## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
+-gpgpu_pipeline_widths 4,1,0,4,1,4,1,0,4,1,9
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
-gpgpu_num_dp_units 1
@@ -74,16 +74,14 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
-# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
-# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres are used
--gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 49152
--gpgpu_shmem_sizeDefault 49152
--gpgpu_shmem_size_PrefL1 49152
--gpgpu_shmem_size_PrefShared 49152
+-gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_sizeDefault 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
# By default, L1 cache is disabled in Pascal P102.
# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
-gmem_skip_L1D 1
@@ -136,7 +134,7 @@
# interconnection
-network_mode 1
--inter_config_file config_fermi_islip.icnt
+-inter_config_file config_pascal_islip.icnt
# memory partition latency config
-rop_latency 120
@@ -168,7 +166,7 @@
#-Write_Queue_Size 64:56:32
# Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 2
+-gpgpu_num_sched_per_core 4
# Two Level Scheduler with active and pending pools
#-gpgpu_scheduler two_level_active:6:0:1
# Loose round robbin scheduler
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config
new file mode 100644
index 0000000..17ad779
--- /dev/null
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim_old.config
@@ -0,0 +1,192 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61
+-gpgpu_ignore_resources_limitation 1
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
+# Compute Capability
+-gpgpu_compute_capability_major 6
+-gpgpu_compute_capability_minor 1
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
+
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32
+-gpgpu_shader_cta 16
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
+-gpgpu_num_dp_units 1
+
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 8,8,8,8,130
+-ptx_opcode_initiation_sfu 4
+-ptx_opcode_latency_sfu 8
+
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 49152
+-gpgpu_shmem_sizeDefault 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
+-gpgpu_flush_l1_cache 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 32:32:32:32
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+# 4 KB Inst.
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+# 48 KB Tex
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 12
+-gpgpu_operand_collector_num_units_sfu 6
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_dp 6
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_dp 1
+-gpgpu_operand_collector_num_out_ports_dp 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+# Use Pascal Coalsce arhitetecture
+-gpgpu_coalesce_arch 61
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+-gpgpu_max_insn_issue_per_warp 2
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+-network_mode 1
+-inter_config_file config_pascal_islip.icnt
+
+# memory partition latency config
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 64
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4 # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing, scaled to 2500MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
+ CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
+
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Pascal 102 has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Pascal 102
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 584ef8d..41aea78 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -165,7 +165,7 @@
-gpgpu_dram_burst_length 2
-dram_data_command_freq_ratio 2 # HBM is DDR
-gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
# Timing for 1 GHZ
diff --git a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
index 0d4a812..ba50287 100644
--- a/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100_SASS/gpgpusim.config
@@ -20,7 +20,6 @@
-gpgpu_runtime_sync_depth_limit 2
-gpgpu_runtime_pending_launch_count_limit 2048
-gpgpu_kernel_launch_latency 5000
--gpgpu_TB_launch_latency 0
# Compute Capability
-gpgpu_compute_capability_major 7
@@ -166,7 +165,7 @@
-gpgpu_dram_burst_length 2
-dram_data_command_freq_ratio 2 # HBM is DDR
-gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
# Timing for 1 GHZ
diff --git a/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt
new file mode 100644
index 0000000..dec4789
--- /dev/null
+++ b/configs/tested-cfgs/Turing_RTX2060/config_pascal_islip.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40;
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters = 1;
+
+credit_delay = 0;
+routing_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup = 1;
+output_speedup = 1;
+internal_speedup = 2.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config b/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config
new file mode 100644
index 0000000..ab324d8
--- /dev/null
+++ b/configs/tested-cfgs/Turing_RTX2060/gpgpusim.config
@@ -0,0 +1,186 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+-gpgpu_kernel_launch_latency 5000
+-gpgpu_TB_launch_latency 0
+
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 30
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Turing clock domains are adopted from
+# https://en.wikipedia.org/wiki/GeForce_20_series
+-gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0
+# boost mode
+# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_registers_per_block 65536
+-gpgpu_occupancy_sm_number 70
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+-ptx_opcode_latency_sfu 100
+-ptx_opcode_initiation_sfu 8
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+-adaptive_cache_config 0
+-l1_banks 4
+-gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_sizeDefault 65536
+-gpgpu_shmem_per_block 65536
+-gmem_skip_L1D 0
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 20
+-smem_latency 20
+-gpgpu_flush_l1_cache 1
+
+# 32 sets, each 128 bytes 32-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache
+-gpgpu_cache:dl2 S:32:128:32,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
+-gpgpu_dram_partition_queues 64:64:64:64
+-perf_sim_memcpy 1
+-memory_partition_indexing 0
+
+# 128 KB Inst.
+-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
+# 128 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
+-perfect_inst_const_cache 1
+
+# i.e. schedulers are isolated
+-sub_core_model 1
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 32
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+-gpgpu_coalesce_arch 60
+
+## In Volta, a warp scheduler can issue 1 inst per cycle
+-gpgpu_max_insn_issue_per_warp 1
+-gpgpu_dual_issue_diff_exec_units 1
+
+# interconnection
+#-network_mode 1
+#-inter_config_file config_volta_islip.icnt
+# for local xbar, use:
+-network_mode 2
+-inct_in_buffer_limit 512
+-inct_out_buffer_limit 512
+-inct_subnets 2
+-arbiter_algo 1
+
+# memory partition latency config
+-rop_latency 160
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 192
+
+# GDDR6
+# http://monitorinsider.com/GDDR6.html
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 2
+-gpgpu_dram_burst_length 16
+-dram_data_command_freq_ratio 4 # GDDR6 is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing, scaled to 3500MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=4:RRD=10:RCD=20:RAS=50:RP=20:RC=62:
+ CL=20:WL=8:CDLR=9:WR=20:nbkgrp=4:CCDL=4:RTPL=4"
+
+# select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
+# Volta has four schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs, disable it untill we create a real energy model for Volta
+-power_simulation_enabled 0
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 7f9985e..4e38f67 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -573,6 +573,9 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
option_parser_register(opp, "-trace_driven_mode", OPT_BOOL,
&trace_driven_mode, "Turn on trace_driven_mode",
"0");
+ option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL,
+ &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode",
+ "0");
option_parser_register(opp, "-trace", OPT_CSTR,
&g_traces_filename, "traces kernel file"
"traces kernel file directory",
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 1ac4fdb..abc905e 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -348,7 +348,8 @@ public:
size_t sync_depth_limit() const {return runtime_sync_depth_limit; }
size_t pending_launch_count_limit() const {return runtime_pending_launch_count_limit;}
- unsigned is_trace_driven_mode() const { return trace_driven_mode; }
+ bool is_trace_driven_mode() const { return trace_driven_mode; }
+ bool is_skip_first_kernel() const { return trace_skip_first_kernel; }
char* get_traces_filename() const { return g_traces_filename; }
bool flush_l1() const { return gpgpu_flush_l1_cache; }
@@ -408,6 +409,7 @@ private:
//trace driven mode options
bool trace_driven_mode;
+ bool trace_skip_first_kernel;
char *g_traces_filename;
friend class gpgpu_sim;
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index 68b2ff7..0e3aced 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -50,6 +50,7 @@ int main ( int argc, const char **argv )
trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context);
std::vector<std::string> commandlist = tracer.parse_kernellist_file();
+ bool first_kernel=true;
for(unsigned i=0; i<commandlist.size(); ++i) {
@@ -64,6 +65,11 @@ int main ( int argc, const char **argv )
continue;
}
else {
+ //skip the first unimportant initialization kernel
+ if(m_gpgpu_sim->get_config().is_skip_first_kernel() && first_kernel) {
+ first_kernel = false;
+ continue;
+ }
kernel_info = tracer.parse_kernel_info(commandlist[i]);
m_gpgpu_sim->launch(kernel_info);
}
diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h
new file mode 100644
index 0000000..f85346f
--- /dev/null
+++ b/src/trace-driven/kepler_opcode.h
@@ -0,0 +1,141 @@
+//developed by Mahmoud Khairy, Purdue Univ
+//[email protected]
+
+#ifndef KEPLER_OPCODE_H
+#define KEPLER_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include "trace_opcode.h"
+#include <unordered_map>
+#include <string>
+
+#define KEPLER_BINART_VERSION 35
+#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
+
+//TO DO: moving this to a yml or def files
+
+///Kepler ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<std::string,OpcodeChar> Kepler_OpcodeMap = {
+ //Floating Point 32 Instructions
+ {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+ {"FADD", OpcodeChar(OP_FADD, SP_OP)},
+ {"FCMP", OpcodeChar(OP_FCMP, SP_OP)},
+ {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+ {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+ {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)},
+ {"FSET", OpcodeChar(OP_FSET, SP_OP)},
+ {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+ {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+ {"RRO", OpcodeChar(OP_RRO, SP_OP)},
+ //SFU
+ {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
+
+
+ //Double Point Instructions
+ {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+ {"DADD", OpcodeChar(OP_DADD, DP_OP)},
+ {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+ {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)},
+ {"DSET", OpcodeChar(OP_DSET, DP_OP)},
+ {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+ //Integer Instructions
+ {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+ {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
+ {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+ {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+ {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+ {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)},
+ {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+ {"BFE", OpcodeChar(OP_BFE, INTP_OP)},
+ {"BFI", OpcodeChar(OP_BFI, INTP_OP)},
+ {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+ {"SHL", OpcodeChar(OP_SHL, INTP_OP)},
+ {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+ {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+ {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
+ {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)},
+ {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+
+ //Conversion Instructions
+ {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+ {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+ {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+ {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+
+ //Movement Instructions
+ {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+ {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+ {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+ {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+ {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+ //Predicate Instructions
+ {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+ {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+ {"CSET", OpcodeChar(OP_CSET, ALU_OP)},
+ {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+ {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+
+ //Texture Instructions
+ //For now, we ignore texture loads, consider it as ALU_OP
+ {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+ {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+ {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+ {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+ //Load/Store Instructions
+ //For now, we ignore constant loads, consider it as ALU_OP, TO DO
+ {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
+ {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+ {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+ {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+ {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+ {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)},
+ {"ST", OpcodeChar(OP_ST, STORE_OP)},
+ {"STL", OpcodeChar(OP_STL, STORE_OP)},
+ {"STS", OpcodeChar(OP_STS, STORE_OP)},
+ {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)},
+ {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+ {"RED", OpcodeChar(OP_RED, STORE_OP)},
+ {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+ {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+ {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+
+ //surface memory instructions
+ {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)},
+ {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)},
+ {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)},
+ {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)},
+ {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)},
+
+ //Control Instructions
+ {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+ {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+ {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+ {"CAL", OpcodeChar(OP_CAL, CALL_OPS)},
+ {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)},
+ {"RET", OpcodeChar(OP_RET, RET_OPS)},
+ {"BRK", OpcodeChar(OP_BRK, RET_OPS)},
+ {"CONT", OpcodeChar(OP_CONT, RET_OPS)},
+ {"SSY", OpcodeChar(OP_SSY, RET_OPS)},
+ {"PBK", OpcodeChar(OP_PBK, RET_OPS)},
+ {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)},
+ {"PRET", OpcodeChar(OP_PRET, RET_OPS)},
+ {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+ {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
+
+ //Miscellaneous Instructions
+ {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
+ {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+ {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+ {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+ {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+};
+
+#endif
diff --git a/src/trace-driven/pascal_opcode.h b/src/trace-driven/pascal_opcode.h
index d4f787d..2cacb28 100644
--- a/src/trace-driven/pascal_opcode.h
+++ b/src/trace-driven/pascal_opcode.h
@@ -70,6 +70,7 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
{"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
{"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
{"LEA", OpcodeChar(OP_LEA, INTP_OP)},
{"LOP", OpcodeChar(OP_LOP, INTP_OP)},
{"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
@@ -85,6 +86,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
{"SHL", OpcodeChar(OP_SHL, INTP_OP)},
{"XMAD", OpcodeChar(OP_XMAD, INTP_OP)},
+ {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)},
+
//Conversion Instructions
{"F2F", OpcodeChar(OP_F2F, ALU_OP)},
@@ -109,7 +112,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"R2P", OpcodeChar(OP_R2P, ALU_OP)},
{"CSET", OpcodeChar(OP_CSET, ALU_OP)},
{"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+
//Load/Store Instructions
{"LD", OpcodeChar(OP_LD, LOAD_OP)},
@@ -157,6 +161,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
{"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
{"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)},
+ {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)},
{"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
{"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
{"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
index fb8afdd..7b5c523 100644
--- a/src/trace-driven/trace_driven.cc
+++ b/src/trace-driven/trace_driven.cc
@@ -23,6 +23,7 @@
#include "volta_opcode.h"
#include "turing_opcode.h"
#include "pascal_opcode.h"
+#include "kepler_opcode.h"
#include "../gpgpusim_entrypoint.h"
@@ -221,6 +222,10 @@ trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m
OpcodeMap = &Volta_OpcodeMap;
else if(m_binary_verion == PASCAL_TITANX_BINART_VERSION || m_binary_verion == PASCAL_P100_BINART_VERSION)
OpcodeMap = &Pascal_OpcodeMap;
+ else if(m_binary_verion == KEPLER_BINART_VERSION)
+ OpcodeMap = &Kepler_OpcodeMap;
+ else if(m_binary_verion == TURING_BINART_VERSION)
+ OpcodeMap = &Turing_OpcodeMap;
else
assert(0 && "unsupported binary version");
}
diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h
index 2b40ace..d60d0ae 100644
--- a/src/trace-driven/trace_opcode.h
+++ b/src/trace-driven/trace_opcode.h
@@ -10,6 +10,7 @@
enum TraceInstrOpcode {
+ //volta (common insts for others cards as well)
OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP,
OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2,
OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP,
@@ -23,8 +24,12 @@ enum TraceInstrOpcode {
OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX,
OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR,
OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG,
+ //unique insts for pascal
OP_RRO, OP_DMNMX, OP_DSET, OP_BFE, OP_BFI, OP_ICMP, OP_IMADSP, OP_SHL, OP_XMAD, OP_CSET, OP_CSETP,
- OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT,
+ OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, OP_SSY, OP_SYNC, OP_PSET
+ , OP_VMNMX, OP_ISET,
+ //unique insts for kepler
+ OP_FCMP, OP_FSWZ, OP_ISAD, OP_LDSLK, OP_STSCUL, OP_SUCLAMP, OP_SUBFM, OP_SUEAU, OP_SULDGA, OP_SUSTGA,
SASS_NUM_OPCODES /* The total number of opcodes. */
};
typedef enum TraceInstrOpcode sass_op_type;
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 22:25:07 +0000