diff options
26 files changed, 948 insertions, 17 deletions
diff --git a/.travis.yml b/.travis.yml index fabfc5b..6ef6730 100644 --- a/.travis.yml +++ b/.travis.yml @@ -19,5 +19,7 @@ matrix: env: CONFIG=configs.quadro5800.yml - services: docker env: CONFIG=configs.teslac2050.yml + - services: docker + env: CONFIG=configs.gtx1080ti.yml script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" diff --git a/Jenkinsfile b/Jenkinsfile index 2cff7b2..d03e7b9 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -3,6 +3,10 @@ pipeline { label "purdue-cluster" } + options { + disableConcurrentBuilds() + } + stages { stage('simulator-build') { steps { diff --git a/Jenkinsfile.nightly b/Jenkinsfile.nightly new file mode 100644 index 0000000..a8b5fc7 --- /dev/null +++ b/Jenkinsfile.nightly @@ -0,0 +1,77 @@ +pipeline { + agent { + label "purdue-cluster" + } + + triggers { + chron('H H * * *') + } + + stages { + stage('simulator-build') { + steps { + "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone [email protected]:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('2B-insn'){ + steps { + "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p [email protected]:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh [email protected] mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* [email protected]:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: '[email protected]' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: '[email protected]' + } + } +} + @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ + g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so -Wl,--version-script=linux-so-version.txt\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ @@ -161,6 +161,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.1; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib diff --git a/aerialvision/guiclasses.py b/aerialvision/guiclasses.py index 0a7013b..45fed26 100644 --- a/aerialvision/guiclasses.py +++ b/aerialvision/guiclasses.py @@ -69,7 +69,7 @@ import matplotlib matplotlib.use('TkAgg') from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2TkAgg from matplotlib.figure import Figure -from matplotlib import mpl +import matplotlib as mpl from matplotlib.colors import colorConverter from matplotlib import pyplot import Pmw diff --git a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config new file mode 100644 index 0000000..47c2b6a --- /dev/null +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system"> + <!--McPAT will skip the components if number is set to 0 --> + <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported --> + <param name="number_of_cores" value="28"/> + <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined--> + <param name="number_of_L1Directories" value="0"/> + <param name="number_of_L2Directories" value="0"/> + <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports --> + <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters --> + <param name="number_of_NoCs" value="1"/> + <param name="homogeneous_cores" value="1"/><!--1 means homo --> + <param name="homogeneous_L2s" value="1"/> + <param name="homogeneous_L1Directorys" value="1"/> + <param name="homogeneous_L2Directorys" value="1"/> + <param name="homogeneous_L3s" value="1"/> + <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware --> + <param name="homogeneous_NoCs" value="1"/> + <param name="core_tech_node" value="23"/><!-- nm --> + <param name="target_core_clockrate" value="1481"/><!--MHz --> + <param name="temperature" value="380"/> <!-- Kelvin --> + <param name="number_cache_levels" value="2"/> + <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology --> + <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) --> + <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible --> + <param name="machine_bits" value="32"/> + <param name="virtual_address_width" value="32"/> + <param name="physical_address_width" value="32"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 --> + <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/--> + <param name="TOT_INST" value="10" /> + <param name="FP_INT" value="10" /> + <param name="IC_H" value="0.001" /> + <param name="IC_M" value="10" /> + <param name="DC_RH" value="1" /> + <param name="DC_RM" value="1" /> + <param name="DC_WH" value="1" /> + <param name="DC_WM" value="1" /> + <param name="TC_H" value="0.001" /> + <param name="TC_M" value="10" /> + <param name="CC_H" value="4.5071" /> + <param name="CC_M" value="10" /> + <param name="SHRD_ACC" value="10" /> + <param name="REG_RD" value="1.6294" /> + <param name="REG_WR" value="0.5031" /> + <param name="NON_REG_OPs" value="0.01" /> + <param name="SP_ACC" value="10" /> + <param name="SFU_ACC" value="0.0082" /> + <param name="FPU_ACC" value="0.4126" /> + <param name="MEM_RD" value="0.1234" /> + <param name="MEM_WR" value="0.001" /> + <param name="MEM_PRE" value="0.001" /> + <param name="L2_RH" value="100" /> + <param name="L2_RM" value="100" /> + <param name="L2_WH" value="100" /> + <param name="L2_WM" value="42.6966" /> + <param name="NOC_A" value="100" /> + <param name="PIPE_A" value="44.8085" /> + <param name="IDLE_CORE_N" value="2.0382"/> + <param name="CONST_DYNAMICN" value="5.0005" /> + <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period --> + <stat name="total_cycles" value="total_cycles_match_mcpat"/> + <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> + <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> + <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of + virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank --> + <!-- *********************** cores ******************* --> + <component id="system.core0" name="core0"> + <!-- Core property --> + <param name="clock_rate" value="1481"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="9"/> + <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller + default value is machine_bits, if not set --> + <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO--> + <!-- inorder/OoO --> + <param name="number_hardware_threads" value="32"/> + <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor, + it only may be more than one in SMT processors. BTB ports always equals to fetch ports since + branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> + <param name="fetch_width" value="1"/> + <!-- fetch_width determins the size of cachelines of L1 cache block --> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <!-- decode_width determins the number of ports of the + renaming table (both RAM and CAM) scheme --> + <param name="issue_width" value="2"/> + <!-- issue_width determins the number of ports of Issue window and other logic + as in the complexity effective proccessors paper; issue_width==dispatch_width --> + <param name="commit_width" value="2"/> + <!-- commit_width determins the number of ports of register files --> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="0"/> + <!-- number of branch instructions can be predicted simultannouesl--> + <!-- Current version of McPAT does not distinguish int and floating point pipelines + Theses parameters are reserved for future use.--> + <param name="pipelines_per_core" value="1,1"/> + <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared--> + <param name="pipeline_depth" value="8,8"/> + <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops --> + <!-- issue and exe unit--> + <param name="ALU_per_core" value="32"/> + <!-- contains an adder, a shifter, and a logical unit --> + <param name="MUL_per_core" value="4"/> + <!-- For MUL and Div --> + <param name="FPU_per_core" value="32"/> + <!-- buffer between IF and ID stage --> + <param name="instruction_buffer_size" value="1"/> + <!-- buffer between ID and sche/exe stage --> + <param name="decoded_stream_buffer_size" value="1"/> + <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED--> + <!-- McPAT support 2 types of OoO cores, RS based and physical reg based--> + <param name="instruction_window_size" value="1"/> + <param name="fp_instruction_window_size" value="1"/> + <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 --> + <param name="ROB_size" value="0"/> + <!-- each in-flight instruction has an entry in ROB --> + <!-- registers --> + <!-- SM parameters Added by Syed Gilani --> + <param name="rf_banks" value="32"/> + <param name="simd_width" value="32"/> + <param name="collector_units" value="32"/> + <param name="core_clock_ratio" value="2"/> + <param name="warp_size" value="32"/> + + <param name="archi_Regs_IRF_size" value="65536"/> + <param name="archi_Regs_FRF_size" value="32"/> + <!-- if OoO processor, phy_reg number is needed for renaming logic, + renaming logic is for both integer and floating point insts. --> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <!-- rename logic --> + <param name="rename_scheme" value="0"/> + <!-- can be RAM based(0) or CAM based(1) rename scheme + RAM-based scheme will have free list, status table; + CAM-based scheme have the valid bit in the data field of the CAM + both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions; + Detailed RAT Implementation see TR --> + <param name="register_windows_size" value="0"/> + <!-- how many windows in the windowed register file, sun processors; + no register windowing is used when this number is 0 --> + <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha), + They will always try to exeute out-of-order though. --> + <param name="LSU_order" value="inorder"/> + <param name="store_buffer_size" value="32"/> + <!-- By default, in-order cores do not have load buffers --> + <param name="load_buffer_size" value="32"/> + <!-- number of ports refer to sustainable concurrent memory accesses --> + <param name="memory_ports" value="2"/> + <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer + as well as the ports of Dcache which is connected to LSU --> + <!-- dual-pumped Dcache can be used to save the extra read/write ports --> + <param name="RAS_size" value="1"/> + <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check --> + <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops --> + <stat name="total_instructions" value="total_instructions_match_mcpat"/> + <stat name="int_instructions" value="int_instruction_match_mcpat"/> + <stat name="fp_instructions" value="flt_instruction_match_mcpat"/> + <stat name="branch_instructions" value="branch_instruction_match_mcpat"/> + <stat name="branch_mispredictions" value="0"/> + <stat name="load_instructions" value="load_instruction_match_mcpat"/> + <stat name="store_instructions" value="store_instruction_match_mcpat"/> + <stat name="committed_instructions" value="total_instructions_match_mcpat"/> + <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/> + <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/> + <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous --> + <!-- the following cycle stats are used for heterogeneouse cores only, + please ignore them if homogeneouse cores --> + <stat name="total_cycles" value="total_cycles_match_mcpat"/> + <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> + <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> + <!-- instruction buffer stats --> + <!-- ROB stats, both RS and Phy based OoOs have ROB + performance simulator should capture the difference on accesses, + otherwise, McPAT has to guess based on number of commited instructions. --> + <stat name="ROB_reads" value="263886"/> + <stat name="ROB_writes" value="263886"/> + <!-- RAT accesses --> + <stat name="rename_accesses" value="263886"/> + <stat name="fp_rename_accesses" value="263886"/> + <!-- decode and rename stage use this, should be total ic - nop --> + <!-- Inst window stats --> + <stat name="inst_window_reads" value="263886"/> + <stat name="inst_window_writes" value="263886"/> + <stat name="inst_window_wakeup_accesses" value="263886"/> + <stat name="fp_inst_window_reads" value="263886"/> + <stat name="fp_inst_window_writes" value="263886"/> + <stat name="fp_inst_window_wakeup_accesses" value="263886"/> + <!-- RF accesses --> + <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/> + <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/> + <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/> + <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/> + + <!-- The following stat is for operand collector power - Added by Syed --> + <stat name="non_rf_operands" value="0"/> + + <!-- accesses to the working reg --> + <stat name="function_calls" value="0"/> + <stat name="context_switches" value="0"/> <!--not used in the McPAT --> + <!-- Number of Windowes switches (number of function calls and returns)--> + <!-- Alu stats by default, the processor has one FPU that includes the divider and + multiplier. The fpu accesses should include accesses to multiplier and divider --> + <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/> + <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/> + <stat name="mul_accesses" value="mul_accesses_match_mcpat"/> + <stat name="cdb_alu_accesses" value="0"/> + <stat name="cdb_mul_accesses" value="0"/> + <stat name="cdb_fpu_accesses" value="0"/> + <!-- multiple cycle accesses should be counted multiple times, + otherwise, McPAT can use internal counter for different floating point instructions + to get final accesses. But that needs detailed info for floating point inst mix --> + <!-- currently the performance simulator should + make sure all the numbers are final numbers, + including the explicit read/write accesses, + and the implicite accesses such as replacements and etc. + Future versions of McPAT may be able to reason the implicite access + based on param and stats of last level cache + The same rule applies to all cache access stats too! --> + <!-- following is AF for max power computation. + Do not change them, unless you understand them--> + <stat name="IFU_duty_cycle" value="0.25"/> + <stat name="LSU_duty_cycle" value="0.25"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="0.25"/> + <stat name="ALU_duty_cycle" value="0.9"/> + <stat name="MUL_duty_cycle" value="0.5"/> + <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average --> + <stat name="ALU_cdb_duty_cycle" value="0.9"/> + <stat name="MUL_cdb_duty_cycle" value="0.5"/> + <stat name="FPU_cdb_duty_cycle" value="15"/> + <component id="system.core0.predictor" name="PBT"> + <!-- branch predictor; tournament predictor see Alpha implementation --> + <param name="local_predictor_size" value="10,3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + <!-- These parameters can be combined like below in next version + <param name="load_predictor" value="10,3,1024"/> + <param name="global_predictor" value="4096,2"/> + <param name="predictor_chooser" value="4096,2"/> + --> + </component> + <component id="system.core0.itlb" name="itlb"> + <param name="number_entries" value="1"/> + <stat name="total_accesses" value="0"/> + <stat name="total_misses" value="0"/> + <stat name="conflicts" value="0"/> + <!-- there is no write requests to itlb although writes happen to itlb after miss, + which is actually a replacement --> + </component> + <component id="system.core0.icache" name="icache"> + <!-- there is no write requests to itlb although writes happen to it after miss, + which is actually a replacement --> + <param name="icache_config" value="16384,128,4,1,1,3,8,0"/> + <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> + <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> + <param name="buffer_sizes" value="16, 16, 16,0"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="total_instructions_match_mcpat"/> + <stat name="read_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.dtlb" name="dtlb"> + <param name="number_entries" value="1"/> + <stat name="total_accesses" value="0"/> + <stat name="total_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.ccache" name="ccache"> + <!-- all the buffer related are optional --> + <param name="ccache_config" value="16384,64,2,1,1,3,8,0"/> + <param name="buffer_sizes" value="16, 16, 16, 0"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/> + <stat name="write_accesses" value="0"/> + <stat name="read_misses" value="ccache_read_misses_match_mcpat"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.tcache" name="tcache"> + <!-- all the buffer related are optional --> + <param name="tcache_config" value="49152,128,8,1,1,3,8,0"/> + <param name="buffer_sizes" value="16, 16, 16, 0"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/> + <stat name="write_accesses" value="0"/> + <stat name="read_misses" value="tcache_read_misses_match_mcpat"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <!--model the shared memory by mimicing dcache--> + <component id="system.core0.sharedmemory" name="sharedmemory"> + <!-- all the buffer related are optional --> + <param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/> + <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> + <param name="buffer_sizes" value="16, 16, 16, 16"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/> + <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/> + <stat name="read_misses" value="0"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.dcache" name="dcache"> + <!-- all the buffer related are optional --> + <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/> + <param name="buffer_sizes" value="16, 16, 16, 0"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="dcache_read_access_match_mcpat"/> + <stat name="write_accesses" value="dcache_write_access_match_mcpat"/> + <stat name="read_misses" value="dcache_read_miss_match_mcpat"/> + <stat name="write_misses" value="dcache_write_miss_match_mcpat"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.BTB" name="BTB"> + <!-- all the buffer related are optional --> + <param name="BTB_config" value="8192,4,2,1, 1,3"/> + <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> + </component> + </component> + <component id="system.L1Directory0" name="L1Directory0"> + <param name="Directory_type" value="0"/> + <!--0 cam based shadowed tag. 1 directory cache --> + <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/> + <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> + <param name="buffer_sizes" value="8, 8, 8, 8"/> + <!-- all the buffer related are optional --> + <param name="clockrate" value="1400"/> + <param name="ports" value="1,1,1"/> + <!-- number of r, w, and rw search ports --> + <param name="device_type" value="0"/> + <!-- altough there are multiple access types, + Performance simulator needs to cast them into reads or writes + e.g. the invalidates can be considered as writes --> + <stat name="read_accesses" value="800000"/> + <stat name="write_accesses" value="27276"/> + <stat name="read_misses" value="1632"/> + <stat name="write_misses" value="183"/> + <stat name="conflicts" value="20"/> + <stat name="duty_cycle" value="0.45"/> + </component> + <component id="system.L2Directory0" name="L2Directory0"> + <param name="Directory_type" value="1"/> + <!--0 cam based shadowed tag. 1 directory cache --> + <param name="Dir_config" value="1048576,16,16,1,2, 100"/> + <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> + <param name="buffer_sizes" value="8, 8, 8, 8"/> + <!-- all the buffer related are optional --> + <param name="clockrate" value="1400"/> + <param name="ports" value="1,1,1"/> + <!-- number of r, w, and rw search ports --> + <param name="device_type" value="0"/> + <!-- altough there are multiple access types, + Performance simulator needs to cast them into reads or writes + e.g. the invalidates can be considered as writes --> + <stat name="read_accesses" value="0"/> + <stat name="write_accesses" value="0"/> + <stat name="read_misses" value="0"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + <stat name="duty_cycle" value="0.45"/> + </component> + <component id="system.L20" name="L20"> + <!-- all the buffer related are optional --> + <param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/> + <!-- consider 4-way bank interleaving for Niagara 1 --> + <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> + <param name="buffer_sizes" value="16, 16, 16, 16"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <param name="clockrate" value="2962"/> + <param name="ports" value="1,1,1"/> + <!-- number of r, w, and rw ports --> + <param name="device_type" value="0"/> + <stat name="read_accesses" value="200000"/> + <stat name="write_accesses" value="0"/> + <stat name="read_misses" value="0"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + <stat name="duty_cycle" value="0.5"/> + </component> + +<!--**********************************************************************--> +<component id="system.L30" name="L30"> + <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/> + <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> + <param name="clockrate" value="3500"/> + <param name="ports" value="1,1,1"/> + <!-- number of r, w, and rw ports --> + <param name="device_type" value="0"/> + <param name="buffer_sizes" value="16, 16, 16, 16"/> + <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> + <stat name="read_accesses" value="58824"/> + <stat name="write_accesses" value="27276"/> + <stat name="read_misses" value="1632"/> + <stat name="write_misses" value="183"/> + <stat name="conflicts" value="0"/> + <stat name="duty_cycle" value="0.35"/> + </component> + + +<!--**********************************************************************--> + <component id="system.NoC0" name="noc0"> + <param name="clockrate" value="700"/> + <param name="type" value="1"/> + <!-- 1 NoC, O bus --> + <param name="horizontal_nodes" value="2"/> + <param name="vertical_nodes" value="1"/> + <param name="has_global_link" value="0"/> + <!-- 1 has global link, 0 does not have global link --> + <param name="link_throughput" value="1"/><!--w.r.t clock --> + <param name="link_latency" value="1"/><!--w.r.t clock --> + <!-- througput >= latency --> + <!-- Router architecture --> + <param name="input_ports" value="6"/> + <param name="output_ports" value="6"/> + <param name="virtual_channel_per_port" value="1"/> + <!-- input buffer; in classic routers only input ports need buffers --> + <param name="flit_bits" value="32"/> + <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs--> + <param name="chip_coverage" value="1"/> + <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> + <stat name="total_accesses" value="0"/> + <!-- This is the number of total accesses within the whole network not for each router --> + <stat name="duty_cycle" value="0.6"/> + </component> +<!--**********************************************************************--> +<!--**********************************************************************--> + + <component id="system.mem" name="mem"> + <!-- Main memory property --> + <param name="mem_tech_node" value="23"/> + <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB --> + <param name="peak_transfer_rate" value="3200"/><!--MB/S--> + <param name="internal_prefetch_of_DRAM_chip" value="4"/> + <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...--> + <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property --> + <!-- above numbers can be easily found from Wikipedia --> + <param name="capacity_per_channel" value="4096"/> <!-- MB --> + <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank + Current McPAT assumes single DIMMs are used.--> + <param name="number_ranks" value="2"/> + <param name="num_banks_of_DRAM_chip" value="6"/> + <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B --> + <param name="output_width_of_DRAM_chip" value="8"/> + <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> + <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> + <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 --> + <param name="burstlength_of_DRAM_chip" value="8"/> + <stat name="memory_accesses" value="1052"/> + <stat name="memory_reads" value="1052"/> + <stat name="memory_writes" value="1052"/> + </component> + <component id="system.mc" name="mc"> + <!-- Memeory controllers are for DDR(2,3...) DIMMs --> + <!-- current version of McPAT uses published values for base parameters of memory controller + improvments on MC will be added in later versions. --> + <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> + <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> + <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs --> + <param name="block_size" value="64"/><!--B--> + <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers --> + <!-- current McPAT only supports homogeneous memory controllers --> + <param name="memory_channels_per_mc" value="2"/> + <param name="number_ranks" value="1"/> + <param name="withPHY" value="0"/> + <!-- # of ranks of each channel--> + <param name="req_window_size_per_channel" value="16"/> + <param name="IO_buffer_size_per_channel" value="16"/> + <param name="databus_width" value="32"/> + <param name="addressbus_width" value="32"/> + <param name="PRT_entries" value="32"/> + <!-- # of empirical DRAM model parameter --> + <param name="dram_cmd_coeff" value="0"/> + <param name="dram_act_coeff" value="0"/> + <param name="dram_nop_coeff" value="0"/> + <param name="dram_activity_coeff" value="0"/> + <param name="dram_pre_coeff" value="3.8475e-8f"/> + <param name="dram_rd_coeff" value="7.74707143e-8f"/> + <param name="dram_wr_coeff" value="3.54664286e-8f"/> + <param name="dram_req_coeff" value="0"/> + <param name="dram_const_coeff" value="0"/> + + <!-- McPAT will add the control bus width to the addressbus width automatically --> + <stat name="memory_accesses" value="memory_accesses_match_mcpat"/> + <stat name="memory_reads" value="memory_reads_match_mcpat"/> + <stat name="memory_writes" value="memory_writes_match_mcpat"/> + <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate + the average power per MC or per channel. This is sufficent for most application. + Further trackdown can be easily added in later versions. --> + </component> +<!--**********************************************************************--> + <component id="system.niu" name="niu"> + <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> + <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. + the low bound of clock rate of a 10Gb MAC is 150Mhz --> + <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> + <param name="clockrate" value="350"/> + <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> + <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> + <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth --> + <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate + the average power per nic or per channel. This is sufficent for most application. --> + </component> +<!--**********************************************************************--> + <component id="system.pcie" name="pcie"> + <!-- On chip PCIe controller, including Phy--> + <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. + the low bound of clock rate of a PCIe per lane logic is 120Mhz --> + <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> + <param name="withPHY" value="1"/> + <param name="clockrate" value="350"/> + <param name="number_units" value="0"/> + <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 --> + <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> + <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> + <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate + the average power per pcie controller or per channel. This is sufficent for most application. --> + </component> +<!--**********************************************************************--> + <component id="system.flashc" name="flashc"> + <param name="number_flashcs" value="0"/> + <param name="type" value="1"/> <!-- 1: low power; 0 high performance --> + <param name="withPHY" value="1"/> + <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S --> + <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> + <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> + <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate + the average power per fc or per channel. This is sufficent for most application --> + </component> +<!--**********************************************************************--> + + </component> +</component> diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 0c4744a..857a0ff 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -55,7 +55,11 @@ # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 -gmem_skip_L1D 0 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 0c6c126..3097d19 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -6,6 +6,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -62,7 +63,11 @@ # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 -gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config index 8afdd7f..a5e6736 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -55,7 +55,11 @@ # Pascal GP100 has 64KB Shared memory # Pascal GP100 has 48KB L1 cache -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 -gmem_skip_L1D 0 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 28689ce..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,7 +56,11 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 418a733..729eaec 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -373,4 +373,8 @@ void func_header_info_int(const char* s, int i) g_headerList->getListEnd().addOperand(buff); } } + +void maxnt_id(int x, int y, int z) { + +} #endif //_PTX_PARSER_H_ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..7ee7dbe 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -336,10 +336,19 @@ class _cuda_device_id *GPGPUSim_Init() prop->minor = 2; prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - prop->maxThreadsDim[2] = 512; + if(prop->major >= 2) { + prop->maxThreadsPerBlock = 1024; + prop->maxThreadsDim[0] = 1024; + prop->maxThreadsDim[1] = 1024; + } + else + { + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + } + + prop->maxThreadsDim[2] = 64; prop->maxGridSize[0] = 0x40000000; prop->maxGridSize[1] = 0x40000000; prop->maxGridSize[2] = 0x40000000; @@ -352,6 +361,9 @@ class _cuda_device_id *GPGPUSim_Init() #if (CUDART_VERSION >= 2010) prop->multiProcessorCount = the_gpu->get_config().num_shader(); #endif +#if (CUDART_VERSION >= 4000) + prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); +#endif the_gpu->set_prop(prop); the_device = new _cuda_device_id(the_gpu); } @@ -2092,8 +2104,28 @@ cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + // This flag is implicitly always on (unless you are using the driver API). It is safe for GPGPU-Sim to + // just ignore it. + if ( cudaDeviceMapHost == flags ) { + return g_last_cudaError = cudaSuccess; + } else { + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; + } +} + +size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) { + _cuda_device_id *dev = GPGPUSim_Init(); + struct cudaDeviceProp prop; + + prop = *dev->get_prop(); + + size_t max = prop.maxThreadsPerBlock; + + if ((prop.regsPerBlock / attr->numRegs) < max) + max = prop.regsPerBlock / attr->numRegs; + + return max; } cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) @@ -2106,7 +2138,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con attr->constSizeBytes = kinfo->cmem; attr->localSizeBytes = kinfo->lmem; attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? + if(kinfo->maxthreads > 0) + attr->maxThreadsPerBlock = kinfo->maxthreads; + else + attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr); #if CUDART_VERSION >= 3000 attr->ptxVersion = kinfo->ptx_version; attr->binaryVersion = kinfo->sm_target; diff --git a/linux-so-version.txt b/linux-so-version.txt new file mode 100644 index 0000000..40f775d --- /dev/null +++ b/linux-so-version.txt @@ -0,0 +1,2 @@ +libcudart.so.9.1{ +}; diff --git a/setup_environment b/setup_environment index cd6452e..f6a16c5 100644 --- a/setup_environment +++ b/setup_environment @@ -6,7 +6,11 @@ export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` -GPGPUSIM_BUILD_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Change/ {print $6}'` +#Detect Git branch and commit # +GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` +GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" + echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; if [ ! -n "$CUDA_INSTALL_PATH" ]; then @@ -46,8 +50,6 @@ CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("% if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 9100 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 9ba31d9..c115cdf 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -517,7 +517,14 @@ public: const struct textureReference* get_texref(const std::string &texname) const { std::map<std::string, const struct textureReference*>::const_iterator t=m_NameToTextureRef.find(texname); - assert( t != m_NameToTextureRef.end() ); + if( t == m_NameToTextureRef.end() ) { + // search for :: prefixed names + std::string temp("::" + texname); + t=m_NameToTextureRef.find(temp); + } + + assert(t != m_NameToTextureRef.end()); + return t->second; } const struct cudaArray* get_texarray( const struct textureReference *texref ) const @@ -568,6 +575,7 @@ struct gpgpu_ptx_sim_info int cmem; int gmem; int regs; + unsigned maxthreads; unsigned ptx_version; unsigned sm_target; }; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 169c491..2a478f9 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1161,13 +1161,13 @@ void function_info::finalize( memory_space *param_mem ) // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast<const char*>(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); } unsigned offset = p.get_offset(); - assert(offset == param_address); + //assert(offset == param_address); param->set_address(param_address); param_address += size; } diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..c0c58a6 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -228,7 +228,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); func_header_info_int(",", $4); - func_header_info_int(",", $6); } + func_header_info_int(",", $6); + maxnt_id($2, $4, $6);} | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..ee36957 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio } else { *func_info = new function_info(entry_point); (*func_info)->set_name(name); + (*func_info)->set_maxnt_id(0); m_function_info_lookup[key] = *func_info; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..36ef3d5 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1245,6 +1245,7 @@ public: const struct gpgpu_ptx_sim_info* get_kernel_info () const { + assert (m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } @@ -1252,6 +1253,8 @@ public: m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); + // THIS DEPENDS ON ptxas being called after the PTX is parsed. + m_kernel_info.maxthreads = maxnt_id; } symbol_table *get_symtab() { @@ -1275,7 +1278,11 @@ public: } bool is_entry_point() const { return m_entry_point; } + void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;} + unsigned get_maxnt_id() { return maxnt_id;} + private: + unsigned maxnt_id; unsigned m_uid; unsigned m_local_mem_framesize; bool m_entry_point; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..e5731a8 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c) g_global_symbol_table->set_sm_target(a,b,c); } +void maxnt_id(int x, int y, int z) { + g_func_info->set_maxnt_id(x * y * z); +} + void func_header(const char* a) {} //intentional dummy function void func_header_info(const char* a) {} //intentional dummy function void func_header_info_int(const char* a, int b) {} //intentional dummy function diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..13042e1 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type ); void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +void maxnt_id(int x, int y, int z); //Jin: handle instructino group for cdp void start_inst_group(); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index fb57a1e..2f61322 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); @@ -268,6 +268,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation, + "gpgpu_ignore_resources_limitation (default 0)", + "0"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 905139c..c27d532 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2647,6 +2647,10 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const assert( result <= MAX_CTA_PER_SHADER ); if (result < 1) { printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n"); + if(gpgpu_ignore_resources_limitation) { + printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n"); + return 1; + } abort(); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 9fd1ecb..1d66f7c 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1388,6 +1388,7 @@ struct shader_core_config : public core_config unsigned gpgpu_num_reg_banks; bool gpgpu_reg_bank_use_warp_id; bool gpgpu_local_mem_map; + bool gpgpu_ignore_resources_limitation; unsigned max_sp_latency; unsigned max_sfu_latency; |