diff options
| -rw-r--r-- | CHANGES | 9 | ||||
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 11 | ||||
| -rw-r--r-- | configs/QuadroFX5800/gpgpusim.config | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/dram.cc | 26 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 5 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 13 | ||||
| -rw-r--r-- | version | 2 |
7 files changed, 44 insertions, 23 deletions
@@ -16,6 +16,15 @@ Version 3.1.0+edits (development branch) versus 3.1.0 metric was only reporting the average for memory accesses from the final AerialVision sampling window. Now the metric reports average memory latency for all memory accesses in the entire application run. + - Corrected GDDR5 parameters in Fermi configuration: + - Increased burst length to 8 and changed the address mapping to reflect + 16 banks as suggested by Jungrae + - Decreased DRAM clock to 924MHz from 1848MHz. + - Corrected CAS Latency, Write Latency and other timing constraints. + - Added a new option 'dram_data_command_freq_ratio' to configure the + frequency ratio between the DRAM data bus and command bus. This allows + GPGPU-Sim to support both GDDR3 (data rate = 2X command rate) and GDDR5 + (data rate = 4X command rate). Version 3.1.0 versus 3.0.2 - Support for CUDA 4.0 for both PTX and PTXPlus. diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index 1a63db1..1122bbe 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -12,7 +12,7 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:1400.0:700.0:1848.0 +-gpgpu_clock_domains 700.0:1400.0:700.0:924.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -75,14 +75,17 @@ # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBBCCCC.CCSSSSSS # GDDR5 timing from hynix H5GQ1H24AFR # to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 # {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt 16:2:5:12:28:12:35:10:7:6:12:4:3:2 +# -gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:CL=12: +# WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2 +-gpgpu_dram_timing_opt 16:2:6:12:28:12:40:12:4:5:12:4:3:2 # GDDR3 #-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6:11 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index ad1b022..47d3a64 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -49,6 +49,7 @@ -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 4 +-dram_data_command_freq_ratio 2 # GDDR3 is DDR -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS # GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index c073f0d..7571f02 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -209,7 +209,7 @@ void dram_t::cycle() #ifdef DRAM_VIEWCMD printf("\tDQ: BK%d Row:%03x Col:%03x", cmd->bk, cmd->row, cmd->col + cmd->dqbytes); #endif - cmd->dqbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; /*16 bytes*/ + cmd->dqbytes += m_config->dram_atom_size; if (cmd->dqbytes >= cmd->nbytes) { mem_fetch *data = cmd->data; data->set_status(IN_PARTITION_MC_RETURNQ,gpu_sim_cycle+gpu_tot_sim_cycle); @@ -274,22 +274,22 @@ void dram_t::cycle() rwq->set_min_length(m_config->CL); } rwq->push(bk[j]->mrq); - bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; //16 bytes + bk[j]->mrq->txbytes += m_config->dram_atom_size; CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; + bkgrp[grp]->CCDLc = m_config->tCCDL; RTWc = m_config->tRTW; - bk[j]->RTPc = m_config->BL/2; - bkgrp[grp]->RTPLc = m_config->tRTPL; + bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio; + bkgrp[grp]->RTPLc = m_config->tRTPL; issued = true; n_rd++; - bwutil+= m_config->BL/2; - bwutil_partial += m_config->BL/2; + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; bk[j]->n_access++; #ifdef DRAM_VERIFY PRINT_CYCLE=1; printf("\tRD Bk:%d Row:%03x Col:%03x \n", j, bk[j]->curr_row, - bk[j]->mrq->col+bk[j]->mrq->txbytes-m_config->BL*m_config->busW); + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); #endif // transfer done if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { @@ -309,20 +309,20 @@ void dram_t::cycle() } rwq->push(bk[j]->mrq); - bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; /*16 bytes*/ + bk[j]->mrq->txbytes += m_config->dram_atom_size; CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; + bkgrp[grp]->CCDLc = m_config->tCCDL; WTRc = m_config->tWTR; bk[j]->WTPc = m_config->tWTP; issued = true; n_wr++; - bwutil+=2; - bwutil_partial += m_config->BL/2; + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; #ifdef DRAM_VERIFY PRINT_CYCLE=1; printf("\tWR Bk:%d Row:%03x Col:%03x \n", j, bk[j]->curr_row, - bk[j]->mrq->col+bk[j]->mrq->txbytes-m_config->BL*m_config->busW); + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); #endif // transfer done if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index cffec45..35070d8 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -120,8 +120,11 @@ void memory_config::reg_options(class OptionParser * opp) "default = 4 bytes (8 bytes per cycle at DDR)", "4"); option_parser_register(opp, "-gpgpu_dram_burst_length", OPT_UINT32, &BL, - "Burst length of each DRAM request (default = 4 DDR cycle)", + "Burst length of each DRAM request (default = 4 data bus cycle)", "4"); + option_parser_register(opp, "-dram_data_command_freq_ratio", OPT_UINT32, &data_command_freq_ratio, + "Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)", + "2"); option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt, "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index e77f859..2c0fed8 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -86,9 +86,10 @@ struct memory_config { bk_tag_length = i; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); - tRTW = (CL+(BL/2)+2-WL); - tWTR = (WL+(BL/2)+tCDLR); - tWTP = (WL+(BL/2)+tWR); + tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); + tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + tWTP = (WL+(BL/data_command_freq_ratio)+tWR); + dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition m_address_mapping.init(m_n_mem); m_L2_config.init(); m_valid = true; @@ -128,7 +129,7 @@ struct memory_config { unsigned CL; //CAS latency unsigned WL; //WRITE latency - unsigned BL; //Burst Length in bytes (we're using 4? could be 8) + unsigned BL; //Burst Length in bytes (4 in GDDR3, 8 in GDDR5) unsigned tRTW; //time to switch from read to write unsigned tWTR; //time to switch from write to read unsigned tWTP; //time to switch from write to precharge in the same bank @@ -139,6 +140,10 @@ struct memory_config { unsigned nbk; + unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5) + + unsigned dram_atom_size; // number of bytes transferred per read or write command + linear_to_raw_address_translation m_address_mapping; }; @@ -1,2 +1,2 @@ const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.1.0+edits (development branch)"; -const char *g_gpgpusim_build_string = "$Change: 12865 $"; +const char *g_gpgpusim_build_string = "$Change: 13138 $"; |