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-rw-r--r--CHANGES1
-rw-r--r--src/gpgpu-sim/shader.cc4
-rw-r--r--src/gpgpu-sim/shader.h12
-rw-r--r--src/gpuwattch/cacti/Ucache.cc6
-rw-r--r--src/gpuwattch/cacti/basic_circuit.cc43
-rwxr-xr-xsrc/gpuwattch/cacti/mat.cc48
-rw-r--r--src/gpuwattch/cacti/nuca.cc10
-rw-r--r--src/gpuwattch/cacti/technology.cc30
-rwxr-xr-xsrc/gpuwattch/cacti/uca.cc7
-rw-r--r--src/gpuwattch/core.cc27
-rw-r--r--src/gpuwattch/gpgpu_sim_wrapper.cc1
-rw-r--r--src/gpuwattch/iocontrollers.cc11
-rw-r--r--src/gpuwattch/logic.cc4
-rw-r--r--src/gpuwattch/sharedcache.cc3
14 files changed, 37 insertions, 170 deletions
diff --git a/CHANGES b/CHANGES
index fe73cbc..b92f230 100644
--- a/CHANGES
+++ b/CHANGES
@@ -54,6 +54,7 @@ Version 3.2.1+edits (development branch) versus 3.2.1
extentions to interface with GPGPU-Sim. We applied similar changes to
BookSim 2.0.
- Added the ability to trace all the shader cores in the SHADER_DPRINTF
+- Warning fixes for various CUDA and gcc versions
- Bug Fixes:
- Fixed icnt::full() check using wrong mf size
- Fixed the flit count sent to GPUWattch for atomic operations.
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index fbf9d52..3692c01 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1036,12 +1036,14 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
char* config_string )
: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id )
{
+ unsigned m_prioritization_readin;
int ret = sscanf( config_string,
"warp_limiting:%d:%d",
- (int*)&m_prioritization,
+ &m_prioritization_readin,
&m_num_warps_to_limit
);
assert( 2 == ret );
+ m_prioritization = (scheduler_prioritization_type)m_prioritization_readin;
// Currently only GTO is implemented
assert( m_prioritization == SCHEDULER_PRIORITIZATION_GTO );
assert( m_num_warps_to_limit <= shader->get_config()->max_warps_per_shader );
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index c2775cf..6f31523 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -419,14 +419,18 @@ public:
int id,
char* config_str )
: scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ),
- m_pending_warps()
+ m_pending_warps()
{
+ unsigned inner_level_readin;
+ unsigned outer_level_readin;
int ret = sscanf( config_str,
"two_level_active:%d:%d:%d",
&m_max_active_warps,
- (int*)&m_inner_level_prioritization,
- (int*)&m_outer_level_prioritization );
+ &inner_level_readin,
+ &outer_level_readin);
assert( 3 == ret );
+ m_inner_level_prioritization=(scheduler_prioritization_type)inner_level_readin;
+ m_outer_level_prioritization=(scheduler_prioritization_type)outer_level_readin;
}
virtual ~two_level_active_scheduler () {}
virtual void order_warps();
@@ -447,7 +451,7 @@ protected:
const std::vector< shd_warp_t* >::const_iterator& prioritized_iter );
private:
- std::deque< shd_warp_t* > m_pending_warps;
+ std::deque< shd_warp_t* > m_pending_warps;
scheduler_prioritization_type m_inner_level_prioritization;
scheduler_prioritization_type m_outer_level_prioritization;
unsigned m_max_active_warps;
diff --git a/src/gpuwattch/cacti/Ucache.cc b/src/gpuwattch/cacti/Ucache.cc
index 6f37f1a..e855238 100644
--- a/src/gpuwattch/cacti/Ucache.cc
+++ b/src/gpuwattch/cacti/Ucache.cc
@@ -683,7 +683,6 @@ void filter_data_arr(list<mem_array *> & curr_list)
*/
void solve(uca_org_t *fin_res)
{
- bool is_dram = false;
int pure_ram = g_ip->pure_ram;
bool pure_cam = g_ip->pure_cam;
@@ -718,14 +717,11 @@ void solve(uca_org_t *fin_res)
}
bool is_tag;
- uint32_t ram_cell_tech_type;
// If it's a cache, first calculate the area, delay and power for all tag array partitions.
if (!(pure_ram||pure_cam||g_ip->fully_assoc))
{ //cache
is_tag = true;
- ram_cell_tech_type = g_ip->tag_arr_ram_cell_tech_type;
- is_dram = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram));
init_tech_params(g_ip->F_sz_um, is_tag);
for (uint32_t t = 0; t < nthreads; t++)
@@ -755,8 +751,6 @@ void solve(uca_org_t *fin_res)
// if (!g_ip->fully_assoc)
// {//in the new cacti, cam, fully_associative cache are processed as single array in the data portion
is_tag = false;
- ram_cell_tech_type = g_ip->data_arr_ram_cell_tech_type;
- is_dram = ((ram_cell_tech_type == lp_dram) || (ram_cell_tech_type == comm_dram));
init_tech_params(g_ip->F_sz_um, is_tag);
for (uint32_t t = 0; t < nthreads; t++)
diff --git a/src/gpuwattch/cacti/basic_circuit.cc b/src/gpuwattch/cacti/basic_circuit.cc
index 9aeb4e7..a8ea501 100644
--- a/src/gpuwattch/cacti/basic_circuit.cc
+++ b/src/gpuwattch/cacti/basic_circuit.cc
@@ -736,7 +736,7 @@ double shortcircuit_simple(
double vdd)
{
- double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
+ double p_short_circuit, p_short_circuit_discharge, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_charge_low;//this is actually energy
double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
fo_n = i_on_n/i_on_n_in;
@@ -755,8 +755,6 @@ double shortcircuit_simple(
// t4=t1/t2/t3;
// cout <<t1<<"t1\n"<<t2<<"t2\n"<<t3<<"t3\n"<<t4<<"t4\n"<<fanout<<endl;
- p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
- p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
// t1=pow(((vdd-vt)-vt_to_vdd_ratio),1.5);
// t2=pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
@@ -786,43 +784,6 @@ double shortcircuit(
double vdd)
{
- double p_short_circuit=0, p_short_circuit_discharge;//, p_short_circuit_charge, p_short_circuit_discharge_low, p_short_circuit_discharge_high, p_short_circuit_charge_low, p_short_circuit_charge_high; //this is actually energy
- double fo_n, fo_p, fanout, beta_ratio, vt_to_vdd_ratio;
- double f_alpha, k_v, e, g_v_alpha, h_v_alpha;
-
- fo_n = i_on_n/i_on_n_in;
- fo_p = i_on_p/i_on_p_in;
- fanout = 1;
- beta_ratio = i_on_p/i_on_n;
- vt_to_vdd_ratio = vt/vdd;
- e = 2.71828;
- f_alpha = 1/(velocity_index+2) -velocity_index/(2*(velocity_index+3)) +velocity_index/(velocity_index+4)*(velocity_index/2-1);
- k_v = 0.9/0.8+(vdd-vt)/0.8*log(10*(vdd-vt)/e);
- g_v_alpha = (velocity_index + 1)*pow((1-velocity_index),velocity_index)*pow((1-velocity_index),velocity_index/2)/f_alpha/pow((1-velocity_index-velocity_index),(velocity_index/2+velocity_index+2));
- h_v_alpha = pow(2, velocity_index)*(velocity_index+1)*pow((1-velocity_index),velocity_index)/pow((1-velocity_index-velocity_index),(velocity_index+1));
-
- //p_short_circuit_discharge_low = 10/3*(pow(0.5-vt_to_vdd_ratio,3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
-// p_short_circuit_discharge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_p*fo_p/fanout/beta_ratio;
-// p_short_circuit_charge_low = 10/3*(pow(((vdd-vt)-vt_to_vdd_ratio),3.0)/pow(velocity_index,2.0)/pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio))*c_in*vdd*vdd*fo_n*fo_n/fanout*beta_ratio;
-// double t1, t2, t3, t4, t5;
-// t1=pow(((vdd-vt)-vt_to_vdd_ratio),3);
-// t2=pow(velocity_index,2.0);
-// t3=pow(2.0,3*vt_to_vdd_ratio*vt_to_vdd_ratio);
-// t4=t1/t2/t3;
-//
-// cout <<t1<<"t1\n"<<t2<<"t2\n"<<t3<<"t3\n"<<t4<<"t4\n"<<fanout<<endl;
-//
-//
-// p_short_circuit_discharge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_p/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
-// p_short_circuit_charge_high = pow(((vdd-vt)-vt_to_vdd_ratio),1.5)*c_in*vdd*vdd*fo_n/10/pow(2, 3*vt_to_vdd_ratio+2*velocity_index);
-//
-// p_short_circuit_discharge = 1.0/(1.0/p_short_circuit_discharge_low + 1.0/p_short_circuit_discharge_high);
-// p_short_circuit_charge = 1/(1/p_short_circuit_charge_low + 1/p_short_circuit_charge_high);
-//
-// p_short_circuit = (p_short_circuit_discharge + p_short_circuit_charge)/2;
-//
-// p_short_circuit = p_short_circuit_discharge;
-
- p_short_circuit_discharge = k_v*vdd*vdd*c_in*fo_p*fo_p/((vdd-vt)*g_v_alpha*fanout*beta_ratio/2/k_v + h_v_alpha*fo_p);
+ double p_short_circuit=0;
return (p_short_circuit);
}
diff --git a/src/gpuwattch/cacti/mat.cc b/src/gpuwattch/cacti/mat.cc
index 881223d..dc903da 100755
--- a/src/gpuwattch/cacti/mat.cc
+++ b/src/gpuwattch/cacti/mat.cc
@@ -392,7 +392,6 @@ Mat::Mat(const DynamicParameter & dyn_p)
sa_mux_lev_1_dec->area.get_area() +
sa_mux_lev_2_dec->area.get_area()) * (RWP + ERP + EWP);
- double area_efficiency_mat;
// if (!is_fa)
// {
@@ -400,7 +399,6 @@ Mat::Mat(const DynamicParameter & dyn_p)
area.h = (num_subarrays_per_mat/num_subarrays_per_row)* subarray.area.h + h_non_cell_area;
area.w = num_subarrays_per_row * subarray.area.get_w() + w_non_cell_area;
area.w = (area.h*area.w + area_mat_center_circuitry) / area.h;
- area_efficiency_mat = subarray.area.get_area() * num_subarrays_per_mat * 100.0 / area.get_area();
// cout<<"h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux"<<h_bit_mux_sense_amp_precharge_sa_mux_write_driver_write_mux<<endl;
// cout<<"h_comparators"<<h_comparators<<endl;
@@ -659,11 +657,8 @@ double Mat::compute_cam_delay(double inrisetime)
double out_time_ramp, this_delay;
double Rwire, tf, c_intrinsic, rd, Cwire, c_gate_load;
-
- double Wdecdrivep, Wdecdriven, Wfadriven, Wfadrivep, Wfadrive2n, Wfadrive2p, Wfadecdrive1n, Wfadecdrive1p,
- Wfadecdrive2n, Wfadecdrive2p, Wfadecdriven, Wfadecdrivep, Wfaprechn, Wfaprechp,
- Wdummyn, Wdummyinvn, Wdummyinvp, Wfainvn, Wfainvp, Waddrnandn, Waddrnandp,
- Wfanandn, Wfanandp, Wfanorn, Wfanorp, Wdecnandn, Wdecnandp, W_hit_miss_n, W_hit_miss_p;
+ double Wfaprechp, Wdummyn, Wdummyinvn, Wdummyinvp, Waddrnandn, Waddrnandp,
+ Wfanorn, Wfanorp,W_hit_miss_n, W_hit_miss_p;
double c_matchline_metal, r_matchline_metal, c_searchline_metal, r_searchline_metal, dynSearchEng;
int Htagbits;
@@ -696,25 +691,6 @@ double Mat::compute_cam_delay(double inrisetime)
if (linear_scaling)
{
- Wdecdrivep = 450 * g_ip->F_sz_um;//this was 360 micron for the 0.8 micron process
- Wdecdriven = 300 * g_ip->F_sz_um;//this was 240 micron for the 0.8 micron process
- Wfadriven = 62.5 * g_ip->F_sz_um;//this was 50 micron for the 0.8 micron process
- Wfadrivep = 125 * g_ip->F_sz_um;//this was 100 micron for the 0.8 micron process
- Wfadrive2n = 250 * g_ip->F_sz_um;//this was 200 micron for the 0.8 micron process
- Wfadrive2p = 500 * g_ip->F_sz_um;//this was 400 micron for the 0.8 micron process
- Wfadecdrive1n = 6.25 * g_ip->F_sz_um;//this was 5 micron for the 0.8 micron process
- Wfadecdrive1p = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wfadecdrive2n = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfadecdrive2p = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process
- Wfadecdriven = 62.5 * g_ip->F_sz_um;//this was 50 micron for the 0.8 micron process
- Wfadecdrivep = 125 * g_ip->F_sz_um;//this was 100 micron for the 0.8 micron process
- Wfaprechn = 7.5 * g_ip->F_sz_um;//this was 6 micron for the 0.8 micron process
- Wfainvn = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wfainvp = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfanandn = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfanandp = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process
- Wdecnandn = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wdecnandp = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process
Wfaprechp = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
Wdummyn = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
@@ -730,26 +706,6 @@ double Mat::compute_cam_delay(double inrisetime)
}
else
{
- Wdecdrivep = 450 * g_ip->F_sz_um;//this was 360 micron for the 0.8 micron process
- Wdecdriven = 300 * g_ip->F_sz_um;//this was 240 micron for the 0.8 micron process
- Wfadriven = 62.5 * g_ip->F_sz_um;//this was 50 micron for the 0.8 micron process
- Wfadrivep = 125 * g_ip->F_sz_um;//this was 100 micron for the 0.8 micron process
- Wfadrive2n = 250 * g_ip->F_sz_um;//this was 200 micron for the 0.8 micron process
- Wfadrive2p = 500 * g_ip->F_sz_um;//this was 400 micron for the 0.8 micron process
- Wfadecdrive1n = 6.25 * g_ip->F_sz_um;//this was 5 micron for the 0.8 micron process
- Wfadecdrive1p = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wfadecdrive2n = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfadecdrive2p = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process
- Wfadecdriven = 62.5 * g_ip->F_sz_um;//this was 50 micron for the 0.8 micron process
- Wfadecdrivep = 125 * g_ip->F_sz_um;//this was 100 micron for the 0.8 micron process
- Wfaprechn = 7.5 * g_ip->F_sz_um;//this was 6 micron for the 0.8 micron process
- Wfainvn = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wfainvp = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfanandn = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process
- Wfanandp = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process
- Wdecnandn = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process
- Wdecnandp = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process
-
Wfaprechp = g_tp.w_pmos_bl_precharge;//this was 10 micron for the 0.8 micron process
Wdummyn = g_tp.cam.cell_nmos_w;
Wdummyinvn = 75 * g_ip->F_sz_um;//this was 60 micron for the 0.8 micron process
diff --git a/src/gpuwattch/cacti/nuca.cc b/src/gpuwattch/cacti/nuca.cc
index d963090..9518791 100644
--- a/src/gpuwattch/cacti/nuca.cc
+++ b/src/gpuwattch/cacti/nuca.cc
@@ -142,7 +142,7 @@ Nuca::sim_nuca()
/* temp variables */
int it, ro, wr;
int num_cyc;
- unsigned int i, j, k;
+ unsigned int i, j;
unsigned int r, c;
int l2_c;
int bank_count = 0;
@@ -166,10 +166,9 @@ Nuca::sim_nuca()
double avg_lat, avg_hop, avg_hhop, avg_vhop, avg_dyn_power,
avg_leakage_power;
- double opt_acclat = INF, opt_avg_lat = INF, opt_tot_lat = INF;
+ double opt_acclat = INF;
int opt_rows = 0;
int opt_columns = 0;
- double opt_totno_hops = 0;
double opt_avg_hop = 0;
double opt_dyn_power = 0, opt_leakage_power = 0;
min_values_t minval;
@@ -285,7 +284,7 @@ Nuca::sim_nuca()
* count value.
*/
totno_hops = totno_hhops = totno_vhops = tot_lat = 0;
- k = 1;
+
for (i=0; i<r; i++) {
for (j=0; j<c; j++) {
/*
@@ -331,9 +330,6 @@ Nuca::sim_nuca()
if (curr_acclat < opt_acclat) {
opt_acclat = curr_acclat;
- opt_tot_lat = tot_lat;
- opt_avg_lat = avg_lat;
- opt_totno_hops = totno_hops;
opt_avg_hop = avg_hop;
opt_rows = r;
opt_columns = c;
diff --git a/src/gpuwattch/cacti/technology.cc b/src/gpuwattch/cacti/technology.cc
index 70ab6e6..7067470 100644
--- a/src/gpuwattch/cacti/technology.cc
+++ b/src/gpuwattch/cacti/technology.cc
@@ -207,7 +207,6 @@ void init_tech_params(double technology, bool is_tag)
double c_fringe[NUMBER_TECH_FLAVORS];
double c_junc[NUMBER_TECH_FLAVORS];
double I_on_n[NUMBER_TECH_FLAVORS];
- double I_on_p[NUMBER_TECH_FLAVORS];
double Rnchannelon[NUMBER_TECH_FLAVORS];
double Rpchannelon[NUMBER_TECH_FLAVORS];
double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS];
@@ -266,7 +265,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = (Aggre_proj? 1.9/1.2:2)*0.08e-15;//F/micron
c_junc[0] = (Aggre_proj? 1.9/1.2:2)*1e-15;//F/micron2
I_on_n[0] = 750e-6;//A/micron
- I_on_p[0] = 350e-6;//A/micron
//Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline
nmos_effective_resistance_multiplier = 1.54;
n_to_p_eff_curr_drv_ratio[0] = 2.45;
@@ -337,7 +335,7 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = 0.08e-15;//F/micron
c_junc[0] = 1e-15;//F/micron2
I_on_n[0] = 1076.9e-6;//A/micron
- I_on_p[0] = 712.6e-6;//A/micron
+ //I_on_p[0] = 712.6e-6;//A/micron
//Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline
nmos_effective_resistance_multiplier = 1.54;
n_to_p_eff_curr_drv_ratio[0] = 2.45;
@@ -382,7 +380,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 503.6e-6;
- I_on_p[1] = 235.1e-6;
nmos_effective_resistance_multiplier = 1.92;
n_to_p_eff_curr_drv_ratio[1] = 2.44;
gmp_to_gmn_multiplier[1] =0.88;
@@ -426,7 +423,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[2] = 0.08e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 386.6e-6;
- I_on_p[2] = 209.7e-6;
nmos_effective_resistance_multiplier = 1.77;
n_to_p_eff_curr_drv_ratio[2] = 2.54;
gmp_to_gmn_multiplier[2] = 0.98;
@@ -485,7 +481,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 321.6e-6;
- I_on_p[3] = 203.3e-6;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -532,7 +527,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1094.3e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.62;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -591,7 +585,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = 0.077e-15;
c_junc[0] = 1e-15;
I_on_n[0] = 1197.2e-6;
- I_on_p[0] = 870.8e-6;
nmos_effective_resistance_multiplier = 1.50;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
@@ -636,7 +629,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 519.2e-6;
- I_on_p[1] = 266e-6;
nmos_effective_resistance_multiplier = 1.96;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
@@ -680,7 +672,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[2] = 0.08e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 573.1e-6;
- I_on_p[2] = 340.6e-6;
nmos_effective_resistance_multiplier = 1.82;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
@@ -739,7 +730,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15 ;
I_on_n[3] = 399.8e-6;
- I_on_p[3] = 243.4e-6;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -786,7 +776,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15 ;
I_on_n[3] = 1031e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 2.39;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -845,7 +834,6 @@ void init_tech_params(double technology, bool is_tag)
I_on_n[0] = 2046.6e-6;
//There are certain problems with the ITRS PMOS numbers in MASTAR for 45nm. So we are using 65nm values of
//n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier for 45nm
- I_on_p[0] = I_on_n[0] / 2;//This value is fixed arbitrarily but I_on_p is not being used in CACTI
nmos_effective_resistance_multiplier = 1.51;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
@@ -889,7 +877,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 666.2e-6;
- I_on_p[1] = I_on_n[1] / 2;
nmos_effective_resistance_multiplier = 1.99;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
@@ -933,7 +920,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[2] = 0.073e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 748.9e-6;
- I_on_p[2] = I_on_n[2] / 2;
nmos_effective_resistance_multiplier = 1.76;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
@@ -992,7 +978,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 456e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -1039,7 +1024,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 999.4e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -1099,7 +1083,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = 0.04e-15;
c_junc[0] = 1e-15;
I_on_n[0] = 2211.7e-6;
- I_on_p[0] = I_on_n[0] / 2;
nmos_effective_resistance_multiplier = 1.49;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
@@ -1158,7 +1141,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[1] = 0.053e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 683.6e-6;
- I_on_p[1] = I_on_n[1] / 2;
nmos_effective_resistance_multiplier = 1.99;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
@@ -1203,7 +1185,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[2] = 0.057e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 827.8e-6;
- I_on_p[2] = I_on_n[2] / 2;
nmos_effective_resistance_multiplier = 1.73;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
@@ -1262,7 +1243,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.053e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1055.4e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -1309,7 +1289,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.053e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1024.5e-6;
- I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
@@ -1367,7 +1346,7 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = 0.06e-15;//F/micron
c_junc[0] = 0;//F/micron2
I_on_n[0] = 2626.4e-6;//A/micron
- I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used.
+ //I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used.
nmos_effective_resistance_multiplier = 1.45;
n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in
//"Dynamic" tab of Device workspace.
@@ -1412,7 +1391,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[1] = 0.08e-15;
c_junc[1] = 0;//F/micron2
I_on_n[1] = 727.6e-6;//A/micron
- I_on_p[1] = I_on_n[1] / 2;
nmos_effective_resistance_multiplier = 1.99;
n_to_p_eff_curr_drv_ratio[1] = 2;
gmp_to_gmn_multiplier[1] = 0.99;
@@ -1456,7 +1434,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[2] = 0.08e-15;
c_junc[2] = 0;//F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab
I_on_n[2] = 916.1e-6;//A/micron
- I_on_p[2] = I_on_n[2] / 2;
nmos_effective_resistance_multiplier = 1.73;
n_to_p_eff_curr_drv_ratio[2] = 2;
gmp_to_gmn_multiplier[2] = 1.11;
@@ -1524,7 +1501,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.053e-15;//F/micron
c_junc[3] = 1e-15;//F/micron2
I_on_n[3] = 910.5e-6;//A/micron
- I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used.
nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm.
//
n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm
@@ -1586,7 +1562,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[0] = 0.06e-15;//F/micron MASTAR inputdynamic/3
c_junc[0] = 0;//F/micron2 MASTAR result dynamic
I_on_n[0] = 2768.4e-6;//A/micron
- I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used.
nmos_effective_resistance_multiplier = 1.48;//nmos_effective_resistance_multiplier is the ratio of Ieff to Idsat where Ieff is the effective NMOS current and Idsat is the saturation current.
n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in
//"Dynamic" tab of Device workspace.
@@ -1697,7 +1672,6 @@ void init_tech_params(double technology, bool is_tag)
c_fringe[3] = 0.053e-15;//F/micron
c_junc[3] = 1e-15;//F/micron2
I_on_n[3] = 910.5e-6;//A/micron
- I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used.
nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm.
//
n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm
diff --git a/src/gpuwattch/cacti/uca.cc b/src/gpuwattch/cacti/uca.cc
index 98de312..ed9be49 100755
--- a/src/gpuwattch/cacti/uca.cc
+++ b/src/gpuwattch/cacti/uca.cc
@@ -215,13 +215,6 @@ double UCA::compute_delays(double inrisetime)
{
precharge_delay = 0;
}
-
- double dram_array_availability = 0;
- if (dp.is_dram)
- {
- dram_array_availability = (1 - dp.num_r_subarray * cycle_time / dp.dram_refresh_period) * 100;
- }
-
return outrisetime;
}
diff --git a/src/gpuwattch/core.cc b/src/gpuwattch/core.cc
index 86b36f6..a5c3bf3 100644
--- a/src/gpuwattch/core.cc
+++ b/src/gpuwattch/core.cc
@@ -718,7 +718,7 @@ LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* in
exist(exist_)
{
if (!exist) return;
- int idx, tag, data, size, line, assoc, banks;
+ int idx, tag, data, size, line, assoc;
bool debug= false;
int ldst_opcode = XML->sys.core[ithCore].opcode_width;//16;
@@ -750,7 +750,6 @@ LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* in
size = (int)XML->sys.core[ithCore].sharedmemory.dcache_config[0];
line = (int)XML->sys.core[ithCore].sharedmemory.dcache_config[1];
assoc = (int)XML->sys.core[ithCore].sharedmemory.dcache_config[2];
- banks = (int)XML->sys.core[ithCore].sharedmemory.dcache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
@@ -891,7 +890,6 @@ LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* in
size = (int)XML->sys.core[ithCore].ccache.dcache_config[0];
line = (int)XML->sys.core[ithCore].ccache.dcache_config[1];
assoc = (int)XML->sys.core[ithCore].ccache.dcache_config[2];
- banks = (int)XML->sys.core[ithCore].ccache.dcache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
@@ -1035,7 +1033,6 @@ LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* in
size = (int)XML->sys.core[ithCore].tcache.dcache_config[0];
line = (int)XML->sys.core[ithCore].tcache.dcache_config[1];
assoc = (int)XML->sys.core[ithCore].tcache.dcache_config[2];
- banks = (int)XML->sys.core[ithCore].tcache.dcache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
@@ -1181,7 +1178,6 @@ LoadStoreU::LoadStoreU(ParseXML* XML_interface, int ithCore_, InputParameter* in
size = (int)XML->sys.core[ithCore].dcache.dcache_config[0];
line = (int)XML->sys.core[ithCore].dcache.dcache_config[1];
assoc = (int)XML->sys.core[ithCore].dcache.dcache_config[2];
- banks = (int)XML->sys.core[ithCore].dcache.dcache_config[3];
idx = debug?9:int(ceil(log2(size/line/assoc)));
tag = debug?51:XML->sys.physical_address_width-idx-int(ceil(log2(line))) + EXTRA_TAG_BITS;
interface_ip.specific_tag = 1;
@@ -4827,6 +4823,16 @@ void Core::computeEnergy(bool is_tdp)
double num_units = 4.0;
Pipeline_energy=0;
+ if (XML->sys.homogeneous_cores==1)
+ {
+ rtp_pipeline_coe = coredynp.pipeline_duty_cycle * XML->sys.total_cycles * XML->sys.number_of_cores;
+ }
+ else
+ {
+ rtp_pipeline_coe = coredynp.pipeline_duty_cycle * coredynp.total_cycles;
+ }
+
+
if (is_tdp)
{
ifu->computeEnergy(is_tdp);
@@ -4924,16 +4930,7 @@ void Core::computeEnergy(bool is_tdp)
else
{
- if (XML->sys.homogeneous_cores==1)
- {
- rtp_pipeline_coe = coredynp.pipeline_duty_cycle * XML->sys.total_cycles * XML->sys.number_of_cores;
-
- }
- else
- {
- rtp_pipeline_coe = coredynp.pipeline_duty_cycle * coredynp.total_cycles;
- }
- set_pppm(pppm_t, coredynp.num_pipelines*rtp_pipeline_coe/num_units, coredynp.num_pipelines/num_units, coredynp.num_pipelines/num_units, coredynp.num_pipelines/num_units);
+ set_pppm(pppm_t, coredynp.num_pipelines*rtp_pipeline_coe/num_units, coredynp.num_pipelines/num_units, coredynp.num_pipelines/num_units, coredynp.num_pipelines/num_units);
}
if (ifu->exist)
diff --git a/src/gpuwattch/gpgpu_sim_wrapper.cc b/src/gpuwattch/gpgpu_sim_wrapper.cc
index 13c5b3e..efb3e6b 100644
--- a/src/gpuwattch/gpgpu_sim_wrapper.cc
+++ b/src/gpuwattch/gpgpu_sim_wrapper.cc
@@ -717,7 +717,6 @@ void gpgpu_sim_wrapper::detect_print_steady_state(int position, double init_val)
}else{
// Get current average
double temp_avg = sample_val / (double)samples.size() ;
- double temp_ipc = (init_val-init_inst_val)/ (double) (samples.size()*gpu_stat_sample_freq);
if( abs(proc->rt_power.readOp.dynamic-temp_avg) < gpu_steady_power_deviation){ // Value is within threshold
sample_val += proc->rt_power.readOp.dynamic;
diff --git a/src/gpuwattch/iocontrollers.cc b/src/gpuwattch/iocontrollers.cc
index d6ad19b..7575cc9 100644
--- a/src/gpuwattch/iocontrollers.cc
+++ b/src/gpuwattch/iocontrollers.cc
@@ -75,9 +75,9 @@ NIUController::NIUController(ParseXML *XML_interface,InputParameter* interface_i
{
local_result = init_interface(&interface_ip);
- double frontend_area, phy_area, mac_area, SerDer_area;
+ double frontend_area,mac_area, SerDer_area;
double frontend_dyn, mac_dyn, SerDer_dyn;
- double frontend_gates, mac_gates, SerDer_gates;
+ double frontend_gates, mac_gates;
double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
double NMOS_sizing, PMOS_sizing;
@@ -93,7 +93,6 @@ NIUController::NIUController(ParseXML *XML_interface,InputParameter* interface_i
//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate hard IP @65nm.
//SerDer is very hard to scale
SerDer_area = (1.39 + 0.36) * (interface_ip.F_sz_um/0.065);//* (interface_ip.F_sz_um/0.065);
- phy_area = frontend_area + SerDer_area;
//total area
area.set_area((mac_area + frontend_area + SerDer_area)*1e6);
//Power
@@ -109,7 +108,6 @@ NIUController::NIUController(ParseXML *XML_interface,InputParameter* interface_i
//Cadence ChipEstimate using 65nm
mac_gates = 111700;
frontend_gates = 320000;
- SerDer_gates = 200000;
NMOS_sizing = 5*g_tp.min_w_nmos_;
PMOS_sizing = 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
@@ -137,7 +135,6 @@ NIUController::NIUController(ParseXML *XML_interface,InputParameter* interface_i
mac_gates = 111700;
frontend_gates = 52000;
- SerDer_gates = 199260;
NMOS_sizing = g_tp.min_w_nmos_;
PMOS_sizing = g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
@@ -209,7 +206,7 @@ PCIeController::PCIeController(ParseXML *XML_interface,InputParameter* interface
interface_ip(*interface_ip_)
{
local_result = init_interface(&interface_ip);
- double frontend_area, phy_area, ctrl_area, SerDer_area;
+ double ctrl_area, SerDer_area;
double ctrl_dyn, SerDer_dyn;
double ctrl_gates, SerDer_gates;
double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
@@ -226,11 +223,9 @@ PCIeController::PCIeController(ParseXML *XML_interface,InputParameter* interface
//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate @ 65nm.
ctrl_area = (5.2 + 0.5)/2 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
//Area estimation based on average of die photo from Niagara 2, and Cadence ChipEstimate @ 65nm.
- frontend_area = (5.2 + 0.1)/2 * (interface_ip.F_sz_um/0.065)* (interface_ip.F_sz_um/0.065);
//Area estimation based on average of die photo from Niagara 2 and Cadence ChipEstimate hard IP @65nm.
//SerDer is very hard to scale
SerDer_area = (3.03 + 0.36) * (interface_ip.F_sz_um/0.065);//* (interface_ip.F_sz_um/0.065);
- phy_area = frontend_area + SerDer_area;
//total area
//Power
//Cadence ChipEstimate using 65nm the controller includes everything: the PHY, the data link and transaction layer
diff --git a/src/gpuwattch/logic.cc b/src/gpuwattch/logic.cc
index 78f47cf..106b381 100644
--- a/src/gpuwattch/logic.cc
+++ b/src/gpuwattch/logic.cc
@@ -1054,13 +1054,9 @@ inst_decoder::inst_decoder(
void inst_decoder::inst_decoder_delay_power()
{
- double dec_outrisetime;
- double inrisetime=0, outrisetime;
double pppm_t[4] = {1,1,1,1};
double squencer_passes = x86?2:1;
- outrisetime = pre_dec->compute_delays(inrisetime);
- dec_outrisetime = final_dec->compute_delays(outrisetime);
set_pppm(pppm_t, squencer_passes*num_decoder_segments, num_decoder_segments, squencer_passes*num_decoder_segments, num_decoder_segments);
power = power + pre_dec->power*pppm_t;
set_pppm(pppm_t, squencer_passes*num_decoder_segments, num_decoder_segments*num_decoded_signals,
diff --git a/src/gpuwattch/sharedcache.cc b/src/gpuwattch/sharedcache.cc
index f615240..9d4a045 100644
--- a/src/gpuwattch/sharedcache.cc
+++ b/src/gpuwattch/sharedcache.cc
@@ -56,7 +56,7 @@ SharedCache::SharedCache(ParseXML* XML_interface, int ithCache_, InputParameter*
{
int idx;
int tag, data;
- bool is_default, debug;
+ bool debug;
enum Device_ty device_t;
enum Core_type core_t;
double size, line, assoc, banks;
@@ -72,7 +72,6 @@ SharedCache::SharedCache(ParseXML* XML_interface, int ithCache_, InputParameter*
}
debug = false;
- is_default=true;//indication for default setup
if (XML->sys.Embedded)
{
interface_ip.wt =Global_30;
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 21:28:17 +0000