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-rw-r--r--decuda_to_ptxplus/decudaInst.cc46
-rw-r--r--src/cuda-sim/cuda-sim.cc12
-rw-r--r--src/cuda-sim/instructions.cc52
-rw-r--r--src/cuda-sim/ptx.l1
-rw-r--r--src/cuda-sim/ptx.y2
-rw-r--r--src/cuda-sim/ptx_ir.cc1
6 files changed, 53 insertions, 61 deletions
diff --git a/decuda_to_ptxplus/decudaInst.cc b/decuda_to_ptxplus/decudaInst.cc
index 8b17135..98e8a59 100644
--- a/decuda_to_ptxplus/decudaInst.cc
+++ b/decuda_to_ptxplus/decudaInst.cc
@@ -354,7 +354,7 @@ void decudaInst::printNewPtx()
// Common modifications that apply to all instructions
//
stringListPiece* currentPiece;
- int vectorFlag = 0; //0=default, 1=bb64 type, 2=bb128 type
+ int vectorFlag = 0; //0=default, 1=bb64/ff64 type, 2=bb128 type
// Replace '%clock' with '%halfclock'
currentPiece = m_operands->getListStart();
@@ -393,6 +393,7 @@ void decudaInst::printNewPtx()
// Change .b64 to .bb64 from type modifier list
// Change .b128 to .bb128 from type modifier list
+ // Change .f64 to .ff64 from type modifier list
currentPiece = m_typeModifiers->getListStart();
for(int i=0; (i<m_typeModifiers->getSize())&&(currentPiece!=NULL); i++)
{
@@ -407,6 +408,11 @@ void decudaInst::printNewPtx()
currentPiece->stringText = newText;
vectorFlag = 2;
}
+ if( strcmp(modString, ".f64")==0 ) {
+ const char* newText = ".ff64";
+ currentPiece->stringText = newText;
+ vectorFlag = 1;
+ }
currentPiece = currentPiece->nextString;
}
@@ -416,7 +422,7 @@ void decudaInst::printNewPtx()
currentPiece = m_operands->getListStart();
for(int i=0; (i<m_operands->getSize())&&(currentPiece!=NULL); i++)
{
- char newText[40] = "";
+ char *newText = new char[40];
char *regNumString;
int regNumInt;
@@ -432,8 +438,7 @@ void decudaInst::printNewPtx()
snprintf(newText,40,"{$r%u,$r%u,$r%u,$r%u}", regNumInt+0, regNumInt+1, regNumInt+2, regNumInt+3);
currentPiece->stringText = newText;
- break;
- } else if( modString[0] == '$' && modString[1] == 'o'&& modString[2] == 'f' ) {
+ } /*else if( modString[0] == '$' && modString[1] == 'o'&& modString[2] == 'f' ) {
strcpy(newText, modString);
strtok (newText, "s");
regNumString = strtok (NULL, "s");
@@ -444,7 +449,6 @@ void decudaInst::printNewPtx()
snprintf(newText,40,"{$ofs%u,$ofs%u,$ofs%u,$ofs%u}", regNumInt+0, regNumInt+1, regNumInt+2, regNumInt+3);
currentPiece->stringText = newText;
- break;
} else if( modString[0] == '$' && modString[1] == 'p' ) {
strcpy(newText, modString);
strtok (newText, "p");
@@ -456,7 +460,6 @@ void decudaInst::printNewPtx()
snprintf(newText,40,"{$p%u,$p%u,$p%u,$p%u}", regNumInt+0, regNumInt+1, regNumInt+2, regNumInt+3);
currentPiece->stringText = newText;
- break;
} else if( modString[0] == '$' && modString[1] == 'o' ) {
strcpy(newText, modString);
strtok (newText, "o");
@@ -468,7 +471,6 @@ void decudaInst::printNewPtx()
snprintf(newText,40,"{$o%u,$o%u,$o%u,$o%u}", regNumInt+0, regNumInt+1, regNumInt+2, regNumInt+3);
currentPiece->stringText = newText;
- break;
} else if( modString[0] == '$' && modString[1] == 't'&& modString[2] == 'e' ) {
strcpy(newText, modString);
strtok (newText, "x");
@@ -480,39 +482,11 @@ void decudaInst::printNewPtx()
snprintf(newText,40,"{$tex%u,$tex%u,$tex%u,$tex%u}", regNumInt+0, regNumInt+1, regNumInt+2, regNumInt+3);
currentPiece->stringText = newText;
- break;
- }
+ }*/
currentPiece = currentPiece->nextString;
}
}
- // Predicate modifiers :
- // @$p0.ne and @$p0.neu map to @$p0,
- // $p0.eq, $p0.equ, $p0.ge map to @!$p0
- // Assuming only one modifier for now, only removes the first one
- /*if(m_predicate != "")
- {
- currentPiece = m_predicateModifiers->getListStart();
- char* modString = currentPiece->stringText;
- if( strcmp(modString, ".ne")==0 ||
- strcmp(modString, ".neu")==0 ||
- strcmp(modString, ".gtu")==0 ||
- strcmp(modString, ".ltu")==0 ||
- strcmp(modString, ".sf")==0 ) {
- m_predicateModifiers->remove(0);
- } else if( strcmp(modString, ".eq")==0 ||
- strcmp(modString, ".equ")==0 ||
- strcmp(modString, ".le")==0 ||
- strcmp(modString, ".ge")==0 ||
- strcmp(modString, ".nsf")==0 ) {
- // Insert '!' into predicate
- std::string temp = m_predicate;
- temp.insert(1, "!");
- strcpy(m_predicate, temp.c_str());
- m_predicateModifiers->remove(0);
- }
- }*/
-
//
// Instruction specific modifications
//
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 4326987..9b65c25 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -470,7 +470,7 @@ void ptx_instruction::set_opcode_and_latency()
break;
case DIV_OP:
// Floating point only
- if( get_type() == F32_TYPE || get_type() == F64_TYPE ) {
+ if( get_type() == F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE) {
latency = 10;
initiation_interval = 4;
op = SFU_OP;
@@ -483,7 +483,7 @@ void ptx_instruction::set_opcode_and_latency()
initiation_interval = 5;
op = SFU_OP;
}
- if( get_type() == F32_TYPE || get_type() == F64_TYPE ) {
+ if( get_type() == F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE ) {
op = ALU_SFU_OP;
}
break;
@@ -531,6 +531,7 @@ static unsigned datatype2size( unsigned data_type )
case S64_TYPE:
case U64_TYPE:
case F64_TYPE:
+ case FF64_TYPE:
data_size = 8; break;
case BB128_TYPE:
data_size = 16; break;
@@ -599,10 +600,10 @@ void ptx_instruction::pre_decode()
for ( ; opr != op_iter_end(); opr++, n++ ) { //process operands
const operand_info &o = *opr;
if ( has_dst && n==0 ) {
- if ( o.is_reg() ) { //but is destination an actual register? (seems like it fails if it's a vector)
+ if ( o.is_reg() ) {
out[0] = o.reg_num();
arch_reg[0] = o.arch_reg_num();
- } else if ( o.is_vector() ) { //but is destination an actual register? (seems like it fails if it's a vector)
+ } else if ( o.is_vector() ) {
is_vectorin = 1;
unsigned num_elem = o.get_vect_nelem();
if( num_elem >= 1 ) out[0] = o.reg1_num();
@@ -624,7 +625,7 @@ void ptx_instruction::pre_decode()
}
m++;
} else if ( o.is_vector() ) {
- assert(m == 0); //only support 1 vector operand (for textures) right now
+ //assert(m == 0); //only support 1 vector operand (for textures) right now
is_vectorout = 1;
unsigned num_elem = o.get_vect_nelem();
if( num_elem >= 1 ) in[0] = o.reg1_num();
@@ -980,6 +981,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id )
case S64_TYPE:
case U64_TYPE:
case F64_TYPE:
+ case FF64_TYPE:
inst.data_size = 8; break;
default: assert(0); break;
}
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index ad2eb43..6eeccd5 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -137,7 +137,7 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in
ptx_reg_t result, tmp;
if(op.get_double_operand_type() == 0) {
- if(((opType != BB128_TYPE) && (opType != BB64_TYPE)) || (op.get_addr_space() != undefined_space)) {
+ if(((opType != BB128_TYPE) && (opType != BB64_TYPE) && (opType != FF64_TYPE)) || (op.get_addr_space() != undefined_space)) {
if ( op.is_reg() ) {
result = get_reg( op.get_symbol() );
} else if ( op.is_builtin()) {
@@ -199,7 +199,7 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in
result.u128.high = get_reg( op.vec_symbol(2) ).u32;
result.u128.highest = get_reg( op.vec_symbol(3) ).u32;
} else {
- // bb64
+ // bb64 or ff64
result.bits.ls = get_reg( op.vec_symbol(0) ).u32;
result.bits.ms = get_reg( op.vec_symbol(1) ).u32;
}
@@ -314,6 +314,7 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in
finalResult.f32 = -finalResult.f32;
break;
case F64_TYPE:
+ case FF64_TYPE:
finalResult.f64 = -finalResult.f64;
break;
default:
@@ -444,7 +445,7 @@ void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_
const symbol *name1 = dst.vec_symbol(0);
const symbol *name2 = dst.vec_symbol(1);
- if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE) ) {
+ if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE)||(type==FF64_TYPE) ) {
setValue2.f32 = (setValue.u64==0)?1.0f:0.0f;
} else {
setValue2.u32 = (setValue.u64==0)?0xFFFFFFFF:0;
@@ -510,6 +511,7 @@ void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_
predValue.u64 |= 1;
break;
case F64_TYPE:
+ case FF64_TYPE:
if(setValue.f64 == 0)
predValue.u64 |= 1;
break;
@@ -565,7 +567,7 @@ void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_
set_reg(name3,setValue3);
set_reg(name4,setValue4);
}
- else if (type == BB64_TYPE)
+ else if (type == BB64_TYPE || type == FF64_TYPE)
{
//ptxplus version of storing 64 bit values to registers stores to two adjacent registers
ptx_reg_t setValue2;
@@ -698,7 +700,7 @@ void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case U32_TYPE: d.s32 = my_abs(a.u32); break;
case U64_TYPE: d.s64 = my_abs(a.u64); break;
case F32_TYPE: d.f32 = my_abs(a.f32); break;
- case F64_TYPE: d.f64 = my_abs(a.f64); break;
+ case F64_TYPE: case FF64_TYPE: d.f64 = my_abs(a.f64); break;
default:
printf("Execution error: type mismatch with instruction\n");
assert(0);
@@ -767,7 +769,7 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread )
break;
case F16_TYPE: assert(0); break;
case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break;
- case F64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break;
default: assert(0); break;
}
fesetround( orig_rm );
@@ -1667,6 +1669,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type)
data.f32 = truncf(data.f32);
break;
case F64_TYPE:
+ case FF64_TYPE:
if (data.f64 < 0) data.f64 = ceil(data.f64); //negative
else data.f64 = floor(data.f64); //positive
break;
@@ -1692,7 +1695,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type)
data.f32 = cuda_math::__cuda_nearbyintf(data.f32);
#endif
break;
- case F64_TYPE: data.f64 = round(data.f64); break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = round(data.f64); break;
default: assert(0); break;
}
break;
@@ -1711,7 +1714,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type)
case F32_TYPE:
data.f32 = floorf(data.f32);
break;
- case F64_TYPE: data.f64 = floor(data.f64); break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = floor(data.f64); break;
default: assert(0); break;
}
break;
@@ -1728,7 +1731,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type)
printf("Trying to round an integer??\n"); assert(0); break;
case F16_TYPE: assert(0); break;
case F32_TYPE: data.f32 = ceilf(data.f32); break;
- case F64_TYPE: data.f64 = ceil(data.f64); break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break;
default: assert(0); break;
}
break;
@@ -1745,7 +1748,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type)
data.u32 = 0x7fffffff;
}
}
- if (type == F64_TYPE) {
+ if ((type == F64_TYPE)||(type == FF64_TYPE)) {
if (isnan(data.f64)) {
data.u64 = 0xfff8000000000000ull;
}
@@ -1773,6 +1776,7 @@ void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type)
if (data.f32 < 0.0f) data.f32 = 0.0f; //positive
break;
case F64_TYPE:
+ case FF64_TYPE:
if (data.f64 > 1.0f) data.f64 = 1.0f; //negative
if (data.f64 < 0.0f) data.f64 = 0.0f; //positive
break;
@@ -1831,6 +1835,7 @@ void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread )
data.f32 = -data.f32;
break;
case F64_TYPE:
+ case FF64_TYPE:
data.f64 = -data.f64;
break;
default:
@@ -1917,7 +1922,7 @@ void div_impl( const ptx_instruction *pI, ptx_thread_info *thread )
data.u64 = src1_data.u64 / src2_data.u64; break;
case F16_TYPE: assert(0); break;
case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break;
- case F64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break;
default: assert(0); break;
}
thread->set_operand_value(dst,data, i_type, thread,pI);
@@ -2246,7 +2251,7 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread )
fesetround( orig_rm );
break;
}
- case F64_TYPE: {
+ case F64_TYPE: case FF64_TYPE: {
int orig_rm = fegetround();
switch ( rounding_mode ) {
case RN_OPTION: break;
@@ -2298,7 +2303,7 @@ void max_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case S32_TYPE: d.s32 = MY_MAX_I(a.s32,b.s32); break;
case S64_TYPE: d.s64 = MY_MAX_I(a.s64,b.s64); break;
case F32_TYPE: d.f32 = MY_MAX_F(a.f32,b.f32); break;
- case F64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break;
+ case F64_TYPE: case FF64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break;
default:
printf("Execution error: type mismatch with instruction\n");
assert(0);
@@ -2333,7 +2338,7 @@ void min_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case S32_TYPE: d.s32 = MY_MIN_I(a.s32,b.s32); break;
case S64_TYPE: d.s64 = MY_MIN_I(a.s64,b.s64); break;
case F32_TYPE: d.f32 = MY_MIN_F(a.f32,b.f32); break;
- case F64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break;
+ case F64_TYPE: case FF64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break;
default:
printf("Execution error: type mismatch with instruction\n");
assert(0);
@@ -2351,7 +2356,7 @@ void mov_impl( const ptx_instruction *pI, ptx_thread_info *thread )
const operand_info &src1 = pI->src1();
unsigned i_type = pI->get_type();
- if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) ) {
+ if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) && (i_type != FF64_TYPE) ) {
// pack or unpack operation
unsigned nbits_to_move;
ptx_reg_t tmp_bits;
@@ -2540,7 +2545,7 @@ void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread )
fesetround( orig_rm );
break;
}
- case F64_TYPE: {
+ case F64_TYPE: case FF64_TYPE:{
int orig_rm = fegetround();
switch ( rounding_mode ) {
case RN_OPTION: break;
@@ -2587,7 +2592,7 @@ void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread )
assert(0); break;
case F16_TYPE: assert(0); break;
case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break;
- case F64_TYPE: data.f64 = 0.0f - src1_data.f64; break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break;
default: assert(0); break;
}
@@ -2727,6 +2732,7 @@ void rcp_impl( const ptx_instruction *pI, ptx_thread_info *thread )
data.f32 = 1.0f / src1_data.f32;
break;
case F64_TYPE:
+ case FF64_TYPE:
data.f64 = 1.0f / src1_data.f64;
break;
default:
@@ -2804,6 +2810,7 @@ void rsqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread )
d.f32 = cuda_math::__internal_accurate_fdividef(1.0f, sqrtf(a.f32));
break;
case F64_TYPE:
+ case FF64_TYPE:
if ( a.f32 < 0 ) {
d.u64 = 0;
d.u32 = 0x7fc00000; // NaN
@@ -2850,7 +2857,7 @@ void sad_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case S32_TYPE: SAD(d.s32,a.s32,b.s32,c.s32); break;
case S64_TYPE: SAD(d.s64,a.s64,b.s64,c.s64); break;
case F32_TYPE: SAD(d.f32,a.f32,b.f32,c.f32); break;
- case F64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break;
+ case F64_TYPE: case FF64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break;
default:
printf("Execution error: type mismatch with instruction\n");
assert(0);
@@ -2887,6 +2894,7 @@ bool isFloat(int type)
case F16_TYPE:
case F32_TYPE:
case F64_TYPE:
+ case FF64_TYPE:
return true;
default:
return false;
@@ -3029,6 +3037,7 @@ bool CmpOp( int type, ptx_reg_t a, ptx_reg_t b, unsigned cmpop )
}
break;
case F64_TYPE:
+ case FF64_TYPE:
switch (cmpop) {
case EQ_OPTION: t = (a.f64 == b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break;
case NE_OPTION: t = (a.f64 != b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break;
@@ -3107,7 +3116,7 @@ void set_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case U32_TYPE: a.u32 = my_abs(a.u32); break;
case U64_TYPE: a.u64 = my_abs(a.u64); break;
case F32_TYPE: a.f32 = my_abs(a.f32); break;
- case F64_TYPE: a.f64 = my_abs(a.f64); break;
+ case F64_TYPE: case FF64_TYPE: a.f64 = my_abs(a.f64); break;
default:
printf("Execution error: type mismatch with instruction\n");
assert(0);
@@ -3303,6 +3312,7 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread )
case B32_TYPE:
case U32_TYPE: d.u32 = t?a.u32:b.u32; break;
case F64_TYPE:
+ case FF64_TYPE:
case B64_TYPE:
case U64_TYPE: d.u64 = t?a.u64:b.u64; break;
default: assert(0);
@@ -3328,6 +3338,7 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread )
else
d.f32 = sqrt(a.f32); break;
case F64_TYPE:
+ case FF64_TYPE:
if ( a.f64 < 0 )
d.f64 = nan("");
else
@@ -3447,7 +3458,7 @@ void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread )
data.u64 = src1_data.u64 - src2_data.u64; break;
case F16_TYPE: assert(0); break;
case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break;
- case F64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break;
+ case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break;
default: assert(0); break;
}
@@ -3726,6 +3737,7 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
}
} break;
case F64_TYPE:
+ case FF64_TYPE:
mem->read( tex_array_index, 8, &data1.f64);
if (cuArray->desc.y) {
mem->read( tex_array_index+8, 8, &data2.f64);
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index d54530d..527c625 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -257,6 +257,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE;
\.f16 TC; return F16_TYPE;
\.f32 TC; return F32_TYPE;
\.f64 TC; return F64_TYPE;
+\.ff64 TC; return FF64_TYPE;
\.b8 TC; return B8_TYPE;
\.b16 TC; return B16_TYPE;
\.b32 TC; return B32_TYPE;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 5142f4d..a9cd744 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -118,6 +118,7 @@
%token F16_TYPE
%token F32_TYPE
%token F64_TYPE
+%token FF64_TYPE
%token B8_TYPE
%token B16_TYPE
%token B32_TYPE
@@ -365,6 +366,7 @@ scalar_type: S8_TYPE { add_scalar_type_spec( S8_TYPE ); }
| F16_TYPE { add_scalar_type_spec( F16_TYPE ); }
| F32_TYPE { add_scalar_type_spec( F32_TYPE ); }
| F64_TYPE { add_scalar_type_spec( F64_TYPE ); }
+ | FF64_TYPE { add_scalar_type_spec( FF64_TYPE ); }
| B8_TYPE { add_scalar_type_spec( B8_TYPE ); }
| B16_TYPE { add_scalar_type_spec( B16_TYPE ); }
| B32_TYPE { add_scalar_type_spec( B32_TYPE ); }
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index e52fccd..5529da4 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -854,6 +854,7 @@ unsigned type_info_key::type_decode( int type, size_t &size, int &basic_type )
case F16_TYPE: size=16; basic_type=-1; return 8;
case F32_TYPE: size=32; basic_type=-1; return 9;
case F64_TYPE: size=64; basic_type=-1; return 10;
+ case FF64_TYPE: size=64; basic_type=-1; return 10;
case PRED_TYPE: size=1; basic_type=2; return 11;
case B8_TYPE: size=8; basic_type=0; return 12;
case B16_TYPE: size=16; basic_type=0; return 13;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:27:21 +0000