diff options
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.cc | 13 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.h | 38 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 15 |
4 files changed, 39 insertions, 29 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3fa51ee..3af314c 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -116,7 +116,7 @@ -gpgpu_adaptive_cache_config 1 # Volta unified cache has four banks -gpgpu_l1_banks 4 --gpgpu_cache:dl1 S:1:128:256,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 1c36d22..c6a125d 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -312,15 +312,6 @@ enum cache_request_status tag_array::probe(new_addr_type addr, unsigned &idx, abort(); // if an unreserved block exists, it is either invalid or // replaceable - if (probe_mode && m_config.is_streaming()) { - line_table::const_iterator i = - pending_lines.find(m_config.block_addr(addr)); - assert(mf); - if (!mf->is_write() && i != pending_lines.end()) { - if (i->second != mf->get_inst().get_uid()) return SECTOR_MISS; - } - } - return MISS; } @@ -1060,7 +1051,6 @@ void baseline_cache::fill(mem_fetch *mf, unsigned time) { m_tag_array->fill(e->second.m_cache_index, time, mf); else if (m_config.m_alloc_policy == ON_FILL) { m_tag_array->fill(e->second.m_block_addr, time, mf); - if (m_config.is_streaming()) m_tag_array->remove_pending_line(mf); } else abort(); bool has_atomic = false; @@ -1136,9 +1126,6 @@ void baseline_cache::send_read_request(new_addr_type addr, m_tag_array->access(block_addr, time, cache_index, wb, evicted, mf); m_mshrs.add(mshr_addr, mf); - if (m_config.is_streaming() && m_config.m_cache_type == SECTOR) { - m_tag_array->add_pending_line(mf); - } m_extra_mf_fields[mf] = extra_mf_fields( mshr_addr, mf->get_addr(), cache_index, mf->get_data_size(), m_config); mf->set_data_size(m_config.get_atom_sz()); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 00c09ae..aa0a7e8 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -574,22 +574,26 @@ class cache_config { exit_parse_error(); } if (m_alloc_policy == STREAMING) { - // For streaming cache, we set the alloc policy to be on-fill to remove - // all line_alloc_fail stalls we set the MSHRs to be equal to max - // allocated cache lines. This is possible by moving TAG to be shared - // between cache line and MSHR enrty (i.e. for each cache line, there is - // an MSHR rntey associated with it) This is the easiest think we can - // think about to model (mimic) L1 streaming cache in Pascal and Volta - // Based on our microbenchmakrs, MSHRs entries have been increasing - // substantially in Pascal and Volta For more information about streaming - // cache, see: - // http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - // https://ieeexplore.ieee.org/document/8344474/ + /* + For streaming cache: + (1) we set the alloc policy to be on-fill to remove all line_alloc_fail stalls. + if the whole memory is allocated to the L1 cache, then make the allocation to be on_MISS + otherwise, make it ON_FILL to eliminate line allocation fails. + i.e. MSHR throughput is the same, independent on the L1 cache size/associativity + So, we set the allocation policy per kernel basis, see shader.cc, max_cta() function + + (2) We also set the MSHRs to be equal to max + allocated cache lines. This is possible by moving TAG to be shared + between cache line and MSHR enrty (i.e. for each cache line, there is + an MSHR rntey associated with it). This is the easiest think we can + think of to model (mimic) L1 streaming cache in Pascal and Volta + + For more information about streaming cache, see: + http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + https://ieeexplore.ieee.org/document/8344474/ + */ m_is_streaming = true; m_alloc_policy = ON_FILL; - m_mshr_entries = m_nset * m_assoc * MAX_DEFAULT_CACHE_SIZE_MULTIBLIER; - if (m_cache_type == SECTOR) m_mshr_entries *= SECTOR_CHUNCK_SIZE; - m_mshr_max_merge = MAX_WARP_PER_SM; } switch (mshr_type) { case 'F': @@ -638,7 +642,8 @@ class cache_config { } // detect invalid configuration - if (m_alloc_policy == ON_FILL and m_write_policy == WRITE_BACK) { + if ((m_alloc_policy == ON_FILL || m_alloc_policy == STREAMING) + and m_write_policy == WRITE_BACK) { // A writeback cache with allocate-on-fill policy will inevitably lead to // deadlock: The deadlock happens when an incoming cache-fill evicts a // dirty line, generating a writeback request. If the memory subsystem is @@ -750,6 +755,9 @@ class cache_config { } bool is_streaming() { return m_is_streaming; } FuncCache get_cache_status() { return cache_status; } + void set_allocation_policy(enum allocation_policy_t alloc) { + m_alloc_policy = alloc; + } char *m_config_string; char *m_config_stringPrefL1; char *m_config_stringPrefShared; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index c6e7b8f..0ad9547 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3308,6 +3308,21 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { m_L1D_config.get_total_size_inKB()); } + if(m_L1D_config.is_streaming()) { + //for streaming cache, if the whole memory is allocated + //to the L1 cache, then make the allocation to be on_MISS + //otherwise, make it ON_FILL to eliminate line allocation fails + //i.e. MSHR throughput is the same, independent on the L1 cache size/associativity + if(total_shmed == 0) { + m_L1D_config.set_allocation_policy(ON_MISS); + printf("GPGPU-Sim: Reconfigure L1 allocation to ON_MISS\n"); + } + else { + m_L1D_config.set_allocation_policy(ON_FILL); + printf("GPGPU-Sim: Reconfigure L1 allocation to ON_FILL\n"); + } + } + k.cache_config_set = true; } |