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-rw-r--r--src/gpgpu-sim/shader.cc5
-rw-r--r--src/gpgpu-sim/shader.h3
2 files changed, 6 insertions, 2 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 19c2291..50ad5ea 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1089,14 +1089,15 @@ void ldst_unit::writeback()
m_pending_writes[m_next_wb.warp_id()].erase(m_next_wb.out[r]);
m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] );
m_stats->m_num_sim_insn[m_sid]++;
+ m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count();
}
} else { // shared
m_scoreboard->releaseRegister( m_next_wb.warp_id(), m_next_wb.out[r] );
m_stats->m_num_sim_insn[m_sid]++;
+ m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count();
}
}
}
- m_core->get_gpu()->gpu_sim_insn += m_next_wb.active_count();
m_next_wb.clear();
m_last_inst_gpu_sim_cycle = gpu_sim_cycle;
m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle;
@@ -1234,6 +1235,7 @@ void ldst_unit::cycle()
}
}
if( !pending_requests ) {
+ m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count();
m_scoreboard->releaseRegisters(m_dispatch_reg);
m_stats->m_num_sim_insn[m_sid]++;
}
@@ -1243,6 +1245,7 @@ void ldst_unit::cycle()
} else {
// stores exit pipeline here
m_core->dec_inst_in_pipeline(warp_id);
+ m_core->get_gpu()->gpu_sim_insn += m_dispatch_reg->active_count();
m_dispatch_reg->clear();
m_stats->m_num_sim_insn[m_sid]++;
}
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index dcb24be..e7d2f1b 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1110,7 +1110,8 @@ public:
mem_fetch *alloc( const warp_inst_t &inst, const mem_access_t &access ) const
{
warp_inst_t inst_copy = inst;
- inst_copy.set_active(access.get_warp_mask());
+ // tgrogers Oct 27, 2011 - I am commenting out this line of code, because it is screwing up our instruction counts on memory instructions. I am not sure what the point of this was, because no one seems to read the active mask on the memory fetches's warp instruction.
+ //inst_copy.set_active(access.get_warp_mask());
mem_fetch *mf = new mem_fetch(access,
&inst_copy,
access.is_write()?WRITE_PACKET_SIZE:READ_PACKET_SIZE,