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-rw-r--r--configs/Pascal-P100-HBM/gpgpusim.config4
-rw-r--r--configs/Pascal-P102-GDDR5X/gpgpusim.config4
-rw-r--r--configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config4
-rw-r--r--configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config4
-rw-r--r--cuobjdump_to_ptxplus/ptx_parser.h4
-rw-r--r--libcuda/cuda_runtime_api.cc59
-rw-r--r--src/abstract_hardware_model.h10
-rw-r--r--src/cuda-sim/cuda-sim.cc4
-rw-r--r--src/cuda-sim/ptx.y3
-rw-r--r--src/cuda-sim/ptx_ir.cc1
-rw-r--r--src/cuda-sim/ptx_ir.h7
-rw-r--r--src/cuda-sim/ptx_parser.cc4
-rw-r--r--src/cuda-sim/ptx_parser.h1
-rw-r--r--src/gpgpu-sim/gpu-sim.cc2
14 files changed, 86 insertions, 25 deletions
diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config
index 0c4744a..857a0ff 100644
--- a/configs/Pascal-P100-HBM/gpgpusim.config
+++ b/configs/Pascal-P100-HBM/gpgpusim.config
@@ -55,7 +55,11 @@
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# Pascal GP100 has 64KB Shared memory
-gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
-gmem_skip_L1D 0
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config
index 0c6c126..feb8c0b 100644
--- a/configs/Pascal-P102-GDDR5X/gpgpusim.config
+++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config
@@ -62,7 +62,11 @@
# Pascal GP102 has 24KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres is used
-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
-gpgpu_shmem_size 49152
+-gpgpu_shmem_size_PrefL1 49152
+-gpgpu_shmem_size_PrefShared 49152
-gmem_skip_L1D 1
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
index 8afdd7f..a5e6736 100644
--- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config
@@ -55,7 +55,11 @@
# Pascal GP100 has 64KB Shared memory
# Pascal GP100 has 48KB L1 cache
-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16
-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 65536
+-gpgpu_shmem_size_PrefShared 65536
-gmem_skip_L1D 0
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
index 28689ce..f78bd02 100644
--- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
@@ -56,7 +56,11 @@
# Pascal GP102 has 64KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres is used
-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16
-gpgpu_shmem_size 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
-gmem_skip_L1D 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h
index 418a733..729eaec 100644
--- a/cuobjdump_to_ptxplus/ptx_parser.h
+++ b/cuobjdump_to_ptxplus/ptx_parser.h
@@ -373,4 +373,8 @@ void func_header_info_int(const char* s, int i)
g_headerList->getListEnd().addOperand(buff);
}
}
+
+void maxnt_id(int x, int y, int z) {
+
+}
#endif //_PTX_PARSER_H_
diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc
index d8e7832..7ee7dbe 100644
--- a/libcuda/cuda_runtime_api.cc
+++ b/libcuda/cuda_runtime_api.cc
@@ -336,23 +336,19 @@ class _cuda_device_id *GPGPUSim_Init()
prop->minor = 2;
prop->totalGlobalMem = 0x80000000 /* 2 GB */;
prop->memPitch = 0;
+ if(prop->major >= 2) {
+ prop->maxThreadsPerBlock = 1024;
+ prop->maxThreadsDim[0] = 1024;
+ prop->maxThreadsDim[1] = 1024;
+ }
+ else
+ {
+ prop->maxThreadsPerBlock = 512;
+ prop->maxThreadsDim[0] = 512;
+ prop->maxThreadsDim[1] = 512;
+ }
- if(prop->major >= 2) {
- prop->maxThreadsPerBlock = 1024;
- prop->maxThreadsDim[0] = 1024;
- prop->maxThreadsDim[1] = 1024;
- }
- else
- {
- prop->maxThreadsPerBlock = 512;
- prop->maxThreadsDim[0] = 512;
- prop->maxThreadsDim[1] = 512;
- }
-
- prop->maxThreadsDim[2] = 64;
- prop->maxGridSize[0] = 0x40000000;
- prop->maxGridSize[1] = 0x40000000;
- prop->maxGridSize[2] = 0x40000000;
+ prop->maxThreadsDim[2] = 64;
prop->maxGridSize[0] = 0x40000000;
prop->maxGridSize[1] = 0x40000000;
prop->maxGridSize[2] = 0x40000000;
@@ -366,7 +362,7 @@ class _cuda_device_id *GPGPUSim_Init()
prop->multiProcessorCount = the_gpu->get_config().num_shader();
#endif
#if (CUDART_VERSION >= 4000)
- prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core();
+ prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core();
#endif
the_gpu->set_prop(prop);
the_device = new _cuda_device_id(the_gpu);
@@ -2108,8 +2104,28 @@ cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len)
cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags )
{
- cuda_not_implemented(__my_func__,__LINE__);
- return g_last_cudaError = cudaErrorUnknown;
+ // This flag is implicitly always on (unless you are using the driver API). It is safe for GPGPU-Sim to
+ // just ignore it.
+ if ( cudaDeviceMapHost == flags ) {
+ return g_last_cudaError = cudaSuccess;
+ } else {
+ cuda_not_implemented(__my_func__,__LINE__);
+ return g_last_cudaError = cudaErrorUnknown;
+ }
+}
+
+size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) {
+ _cuda_device_id *dev = GPGPUSim_Init();
+ struct cudaDeviceProp prop;
+
+ prop = *dev->get_prop();
+
+ size_t max = prop.maxThreadsPerBlock;
+
+ if ((prop.regsPerBlock / attr->numRegs) < max)
+ max = prop.regsPerBlock / attr->numRegs;
+
+ return max;
}
cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun )
@@ -2122,7 +2138,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con
attr->constSizeBytes = kinfo->cmem;
attr->localSizeBytes = kinfo->lmem;
attr->numRegs = kinfo->regs;
- attr->maxThreadsPerBlock = 0; // from pragmas?
+ if(kinfo->maxthreads > 0)
+ attr->maxThreadsPerBlock = kinfo->maxthreads;
+ else
+ attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr);
#if CUDART_VERSION >= 3000
attr->ptxVersion = kinfo->ptx_version;
attr->binaryVersion = kinfo->sm_target;
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index cec75f9..1b764e2 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -517,7 +517,14 @@ public:
const struct textureReference* get_texref(const std::string &texname) const
{
std::map<std::string, const struct textureReference*>::const_iterator t=m_NameToTextureRef.find(texname);
- assert( t != m_NameToTextureRef.end() );
+ if( t == m_NameToTextureRef.end() ) {
+ // search for :: prefixed names
+ std::string temp("::" + texname);
+ t=m_NameToTextureRef.find(temp);
+ }
+
+ assert(t != m_NameToTextureRef.end());
+
return t->second;
}
const struct cudaArray* get_texarray( const struct textureReference *texref ) const
@@ -568,6 +575,7 @@ struct gpgpu_ptx_sim_info
int cmem;
int gmem;
int regs;
+ unsigned maxthreads;
unsigned ptx_version;
unsigned sm_target;
};
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 2f166aa..3d3a820 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -1159,13 +1159,13 @@ void function_info::finalize( memory_space *param_mem )
// copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over
//Jin: copy parameter using aligned rules
const size_t word_size = 4;
- param_address = (param_address + size - 1) / size * size; //aligned with size
+ //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct
for (size_t idx = 0; idx < size; idx += word_size) {
const char *pdata = reinterpret_cast<const char*>(param_value.pdata) + idx; // cast to char * for ptr arithmetic
param_mem->write(param_address + idx, word_size, pdata,NULL,NULL);
}
unsigned offset = p.get_offset();
- assert(offset == param_address);
+ //assert(offset == param_address);
param->set_address(param_address);
param_address += size;
}
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index e00aa4b..c0c58a6 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -228,7 +228,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement
block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2);
func_header_info_int(",", $4);
- func_header_info_int(",", $6); }
+ func_header_info_int(",", $6);
+ maxnt_id($2, $4, $6);}
| MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); }
| MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); }
;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 8ebdcf8..ee36957 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio
} else {
*func_info = new function_info(entry_point);
(*func_info)->set_name(name);
+ (*func_info)->set_maxnt_id(0);
m_function_info_lookup[key] = *func_info;
}
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 9ad1571..36ef3d5 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1245,6 +1245,7 @@ public:
const struct gpgpu_ptx_sim_info* get_kernel_info () const
{
+ assert (m_kernel_info.maxthreads == maxnt_id);
return &m_kernel_info;
}
@@ -1252,6 +1253,8 @@ public:
m_kernel_info = info;
m_kernel_info.ptx_version = 10*get_ptx_version().ver();
m_kernel_info.sm_target = get_ptx_version().target();
+ // THIS DEPENDS ON ptxas being called after the PTX is parsed.
+ m_kernel_info.maxthreads = maxnt_id;
}
symbol_table *get_symtab()
{
@@ -1275,7 +1278,11 @@ public:
}
bool is_entry_point() const { return m_entry_point; }
+ void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;}
+ unsigned get_maxnt_id() { return maxnt_id;}
+
private:
+ unsigned maxnt_id;
unsigned m_uid;
unsigned m_local_mem_framesize;
bool m_entry_point;
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index baa3bcd..e5731a8 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c)
g_global_symbol_table->set_sm_target(a,b,c);
}
+void maxnt_id(int x, int y, int z) {
+ g_func_info->set_maxnt_id(x * y * z);
+}
+
void func_header(const char* a) {} //intentional dummy function
void func_header_info(const char* a) {} //intentional dummy function
void func_header_info_int(const char* a, int b) {} //intentional dummy function
diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h
index 32f3903..13042e1 100644
--- a/src/cuda-sim/ptx_parser.h
+++ b/src/cuda-sim/ptx_parser.h
@@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type );
void change_operand_neg( );
void set_immediate_operand_type( );
void version_header(double a);
+void maxnt_id(int x, int y, int z);
//Jin: handle instructino group for cdp
void start_inst_group();
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 17f1714..bb448b3 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
- option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
+ option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 08:07:38 +0000