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Diffstat (limited to 'bsmad_test/bsmad_result.txt')
| -rw-r--r-- | bsmad_test/bsmad_result.txt | 333 |
1 files changed, 333 insertions, 0 deletions
diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt new file mode 100644 index 0000000..968a990 --- /dev/null +++ b/bsmad_test/bsmad_result.txt @@ -0,0 +1,333 @@ +GNU gdb (GDB) SUSE (7.5.1-2.5.1) +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-suse-linux". +For bug reporting instructions, please see: +<http://www.gnu.org/software/gdb/bugs/>... +Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done. +To enable execution of this file add + add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit +line to your configuration file "/home/negargoli93/.gdbinit". +To completely disable this security protection add + set auto-load safe-path / +line to your configuration file "/home/negargoli93/.gdbinit". +For more information about this security protection see the +"Auto-loading safe path" section in the GDB manual. E.g., run from the shell: + info "(gdb)Auto-loading safe path" +(gdb) r^C(gdb) r +Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +[Thread debugging using libthread_db enabled] +Using host libthread_db library "/lib64/libthread_db.so.1". + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)] +[Thread 0x7ffff4512700 (LWP 5117) exited] +[New Thread 0x7ffff4512700 (LWP 5120)] + +Program received signal SIGINT, Interrupt. +0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0 +Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64 +(gdb) +(gdb) quit +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? 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(y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) EOF [assumed Y] |