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-rw-r--r--configs/GTX480/gpgpusim.config18
1 files changed, 10 insertions, 8 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index 436cb41..03fcda1 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -29,10 +29,12 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_pipeline_widths 2,1,1,2,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+#For Fermi, DP unit =0, DP inst is executed on SFU
+-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 1
+-gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
@@ -48,20 +50,20 @@
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
--gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8
-gpgpu_shmem_size 49152
# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
-#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8
+#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8
#-gpgpu_shmem_size 16384
# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32
-gpgpu_cache:dl2_texture_only 0
--gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
--gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
+-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4
+-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6