diff options
Diffstat (limited to 'configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config')
| -rw-r--r-- | configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 40 |
1 files changed, 24 insertions, 16 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 782edf6..4407870 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -21,7 +21,7 @@ #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -32,21 +32,26 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,1,4,4,1,8 +-gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,1,1,1,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo @@ -54,33 +59,36 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 -gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_sfu 4 +-gpgpu_operand_collector_num_out_ports_sfu 4 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 # gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 @@ -97,7 +105,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 100 -dram_latency 100 # dram model config @@ -122,8 +130,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" # Pascal GP102 has four schedulers per core -gpgpu_num_sched_per_core 4 |