diff options
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 5ac734d..7b0369a 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -12,7 +12,6 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 --gpgpu_tensor_core_avail 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -45,10 +44,12 @@ # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE ## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8,1,1 +-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 4 +-gpgpu_tensor_core_avail 1 +-gpgpu_num_tensor_core_units 4 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" |