3 files changed, 23 insertions, 14 deletions
diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
index a788090..0a73c81 100644
--- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt
+++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
@@ -1,13 +1,13 @@
 //21*1 fly with 32 flits per packet under gpgpusim injection mode
 use_map = 0;
-flit_size = 32; 
+flit_size = 40; 
 
 // currently we do not use this, see subnets below
 network_count = 2;
 
 // Topology
 topology = fly;
-k = 62;
+k = 60;
 n = 1;
 
 // Routing
@@ -17,7 +17,10 @@ routing_function = dest_tag;
 // Flow control
 
 num_vcs     = 1;
-vc_buf_size = 8;
+vc_buf_size = 64;
+input_buffer_size = 64;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config
index 5b038de..1029194 100644
--- a/configs/Pascal-P100-HBM/gpgpusim.config
+++ b/configs/Pascal-P100-HBM/gpgpusim.config
@@ -54,13 +54,17 @@
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:128:8,8
+-gpgpu_cache:dl1  S:64:128:6,L:L:m:N:H,A:128:8,32:0,32
 -gpgpu_shmem_size 65536
--gmem_skip_L1D 0
+-gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
 
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32
+# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+#-gpgpu_flush_l2_cache 1
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -89,8 +93,7 @@
 -gpgpu_shmem_num_banks 32
 -gpgpu_shmem_limited_broadcast 0
 -gpgpu_shmem_warp_parts 1
-# Use Fermi Coalscer arhitetecture for now! Need to be canged to pascal Coalscer
--gpgpu_coalesce_arch 20
+-gpgpu_coalesce_arch 60
 
 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
 -gpgpu_max_insn_issue_per_warp 2
@@ -123,10 +126,6 @@
 -gpgpu_mem_address_mask 1
 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
 
-# GDDR5 timing
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
-#                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
-
 # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
 # Timing for 1 GHZ
 # tRRDl and tWTR are missing, need to be added
@@ -140,8 +139,12 @@
 # HBM has dual bus interface, in which it can issue two col and row commands at a time
 -dual_bus_interface 1
 # select lower bits for bnkgrp to increase bnkgrp parallelism
+-dram_bnk_indexing_policy 0
 -dram_bnkgrp_indexing_policy 1
 
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 64:56:32
+
 # Pascal has two schedulers per core
 -gpgpu_num_sched_per_core 2
 # Two Level Scheduler with active and pending pools
@@ -158,7 +161,7 @@
 -visualizer_enabled 0
 
 # power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 1
+-power_simulation_enabled 0
 -gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality
diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
index 58e596d..94b2378 100644
--- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
+++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
@@ -18,6 +18,9 @@ routing_function = dest_tag;
 
 num_vcs     = 1;
 vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
 
 wait_for_tail_credit = 0;