diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 8 | ||||
| -rw-r--r-- | configs/Pascal-P102-GDDR5X/gpgpusim.config | 10 |
2 files changed, 9 insertions, 9 deletions
diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt index 94b2378..714d933 100644 --- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt +++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt @@ -17,10 +17,10 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 32; -input_buffer_size = 32; -ejection_buffer_size = 32; -boundary_buffer_size = 32; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; wait_for_tail_credit = 0; diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 257560e..cb69767 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -61,7 +61,7 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 N:32:128:6,L:L:m:N:H,S:128:8,16 +-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gmem_skip_L1D 1 -icnt_flit_size 40 @@ -71,7 +71,7 @@ -gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -#-gpgpu_flush_l2_cache 1 +-perf_sim_memcpy 1 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -113,7 +113,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 0 +-rop_latency 100 -dram_latency 100 # dram model config @@ -138,8 +138,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 |