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-rw-r--r--configs/tested-cfgs/SM2_GTX480/gpgpusim.config7
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config18
-rw-r--r--configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt2
-rw-r--r--configs/tested-cfgs/SM7_TITANV/gpgpusim.config75
4 files changed, 48 insertions, 54 deletions
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 4096b09..d71b2fd 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -30,9 +30,10 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-#For Fermi, DP unit =0, DP inst is executed on SFU
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+# For Fermi, DP unit =0, DP inst is executed on SFU
+# For Fermi, INT unit =0, INT inst is executed on SP
+-gpgpu_pipeline_widths 2,0,0,1,1,2,0,0,1,1,2
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 1
-gpgpu_num_dp_units 0
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 3842508..cb23ab3 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -35,10 +35,11 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 2
-gpgpu_num_dp_units 1
@@ -86,6 +87,7 @@
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 32:32:32:32
-perf_sim_memcpy 1
+-memory_partition_indexing 0
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -131,13 +133,8 @@
# dram model config
-gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles). I.e.
-# Total buffer space required = 100 x 924MHz / 700MHz = 132
-gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 240
+-gpgpu_dram_return_queue_size 64
# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
@@ -149,7 +146,7 @@
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-# Use the same GDDR5 timing
+# Use the same GDDR5 timing, scaled to 2500MHZ
-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
@@ -176,7 +173,6 @@
# power model configs, disable it untill we create a real energy model for Pascal 102
-power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
# tracing functionality
#-trace_enabled 1
diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
index 2f25889..615d0a9 100644
--- a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
// Topology
topology = fly;
-k = 64;
+k = 88;
n = 1;
// Routing
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 7532c01..8ed4cd0 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -1,5 +1,5 @@
# This config models the Volta Titan X
-# For more info about this card:
+# For more info about volta architecture:
# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1#
# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
@@ -12,7 +12,6 @@
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 70
--gpgpu_tensor_core_avail 1
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
@@ -22,15 +21,15 @@
-gpgpu_n_clusters 40
-gpgpu_n_cores_per_cluster 2
-gpgpu_n_mem 24
--gpgpu_n_sub_partition_per_mchannel 1
+-gpgpu_n_sub_partition_per_mchannel 2
# volta clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA GV100 clock domains are adopted from
+# Volta NVIDIA V100 clock domains are adopted from
# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
# boost mode
-# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0
# shader core pipeline config
-gpgpu_shader_registers 65536
@@ -42,13 +41,17 @@
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12,1,1
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
-gpgpu_num_sp_units 4
-gpgpu_num_sfu_units 4
-gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
+
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
# All Div operations are executed on SFU unit
@@ -62,7 +65,8 @@
-ptx_opcode_initiation_dp 4,4,4,4,130
-ptx_opcode_latency_sfu 100
-ptx_opcode_initiation_sfu 8
-
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
@@ -72,6 +76,8 @@
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
# disable this mode in case of multi kernels/apps execution
-adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
-gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_shmem_size 98304
-gmem_skip_L1D 0
@@ -81,11 +87,12 @@
-smem_latency 19
-gpgpu_flush_l1_cache 1
-# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
--gpgpu_cache:dl2_texture_only 0
+# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache
+-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 64:64:64:64
-perf_sim_memcpy 1
+-memory_partition_indexing 0
# 128 KB Inst.
-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
@@ -95,20 +102,16 @@
# 64 KB Const
-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
-# enable operand collector
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 0
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
+-gpgpu_num_reg_banks 8
# shared memory bankconflict detection
-gpgpu_shmem_num_banks 32
@@ -116,7 +119,7 @@
-gpgpu_shmem_warp_parts 1
-gpgpu_coalesce_arch 60
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+## In Volta, a warp scheduler can issue 1 inst per cycle
-gpgpu_max_insn_issue_per_warp 1
-gpgpu_dual_issue_diff_exec_units 1
@@ -130,21 +133,16 @@
# dram model config
-gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles). I.e.
-# Total buffer space required = 100 x 924MHz / 700MHz = 132
-gpgpu_frfcfs_dram_sched_queue_size 64
-gpgpu_dram_return_queue_size 192
-# for HBM, 32 channles, each (128 bits) 16 bytes width
+# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width
-gpgpu_n_mem_per_ctrlr 1
-gpgpu_dram_buswidth 16
-gpgpu_dram_burst_length 2
-dram_data_command_freq_ratio 2 # HBM is DDR
-gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS
# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
# Timing for 1 GHZ
@@ -152,9 +150,9 @@
#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
- CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
+ CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
# HBM has dual bus interface, in which it can issue two col and row commands at a time
-dual_bus_interface 1
@@ -182,7 +180,6 @@
# power model configs, disable it untill we create a real energy model for Pascal 100
-power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
# tracing functionality
#-trace_enabled 1
generated by cgit v1.3 (git 2.53.0) at 2026-07-14 05:24:04 +0000