4 files changed, 178 insertions, 0 deletions
diff --git a/configs/ISPASS-2009/gpgpusim.config b/configs/ISPASS-2009/gpgpusim.config
new file mode 100644
index 0000000..b6d1ec1
--- /dev/null
+++ b/configs/ISPASS-2009/gpgpusim.config
@@ -0,0 +1,32 @@
+-gpgpu_interwarp_mshr_merge 6
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_partial_write_mask 1
+-gpgpu_shmem_port_per_bank 2
+-gpgpu_cache_port_per_bank 2
+-gpgpu_const_port_per_bank 2
+-gpgpu_shmem_bkconflict 1
+-gpgpu_n_cache_bank 1
+-gpgpu_cache_bkconflict 1
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_pdom_sched_type 8
+-gpgpu_shader_registers 16768 
+-gpgpu_shader_cta 8
+-gpgpu_cuda_sim
+-gpgpu_shader_core_pipeline  1024:32:32
+
+-gpgpu_mem_address_mask 1
+-gpgpu_pre_mem_stages 1
+-gpgpu_dram_sched_queue_size 32
+-gpgpu_spread_blocks_across_cores
+-network_mode 1
+-gpgpu_simd_model 1 
+-gpgpu_clock_domains 500.0:2000.0:2000.0:2000.0
+
+-gpgpu_dram_scheduler 1
+-gpgpu_cache:dl1 128:64:4:L 
+-gpgpu_no_dl1 
+-gpgpu_n_shader 28 -gpgpu_n_mem 8  
+-gpgpu_dram_buswidth 4  
+
+-inter_config_file mesh
diff --git a/configs/ISPASS-2009/mesh b/configs/ISPASS-2009/mesh
new file mode 100644
index 0000000..b91f18c
--- /dev/null
+++ b/configs/ISPASS-2009/mesh
@@ -0,0 +1,44 @@
+use_map=1;
+flit_size = 16; 
+network_count = 2;
+
+topology = mesh;
+k = 6;
+n = 2;
+
+// Routing
+routing_function = dim_order;
+
+// Flow control
+num_vcs     = 2;  
+vc_buf_size = 4; 
+wait_for_tail_credit = 1;
+
+// Router architecture
+vc_allocator = islip; 
+sw_allocator = islip; 
+alloc_iters  = 1;
+
+credit_delay   = 1;
+routing_delay  = 1;
+vc_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic
+traffic    = gpgpusim; 
+//not used in gpgpusim
+injection_process = gpgpu_injector;
+// Simulation 
+//not used in gpgpusim
+sim_type       = latency;
+injection_rate = 0.1;
+
+
+//STATS
+MATLAB_OUTPUT = 0;		// output data in MATLAB friendly format
+DISPLAY_LAT_DIST    = 0; 	// distribution of packet latencies
+DISPLAY_HOP_DIST   = 0;		// distribution of hop counts
+DISPLAY_PAIR_LATENCY = 0;
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
new file mode 100644
index 0000000..e3d3f9a
--- /dev/null
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -0,0 +1,53 @@
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_cuda_sim
+
+# high level architecture configuration
+-gpgpu_n_shader 30 -gpgpu_n_mem 8 -gpgpu_clock_domains 325.0:650.0:650.0:800.0 
+-gpgpu_spread_blocks_across_cores
+
+# shader core pipeline config
+-gpgpu_shader_registers 16384
+-gpgpu_shader_core_pipeline 1024:32:32 
+-gpgpu_shader_cta 8
+-gpgpu_pre_mem_stages 1
+-gpgpu_pdom_sched_type 8
+-gpgpu_simd_model 1 
+
+# memory stage behaviour
+-gpgpu_no_dl1 1 
+-gpgpu_shmem_bkconflict 1
+-gpgpu_cache_bkconflict 1
+-gpgpu_n_cache_bank 1
+-gpgpu_shmem_pipe_speedup 2
+-gpgpu_shmem_port_per_bank 2
+-gpgpu_cache_port_per_bank 2
+-gpgpu_const_port_per_bank 2
+-gpgpu_interwarp_mshr_merge 6
+-gpgpu_cache:dl1 128:64:4:L 
+-gpgpu_tex_cache:l1 64:64:2:L -gpgpu_const_cache:l1 64:64:2:L 
+
+# interconnection
+-network_mode 1 
+-inter_config_file icnt_config_quadro_islip.txt 
+-gpu_concentration 3 
+
+# dram model config
+-gpgpu_dram_scheduler 1
+-gpgpu_dram_sched_queue_size 32
+-gpgpu_n_mem_per_ctrlr 2
+-gpgpu_dram_buswidth 4 
+-gpgpu_dram_burst_length 4
+-gpgpu_partial_write_mask 1
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
+# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz 
+# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tWTR}
+-gpgpu_dram_timing_opt 8:2:8:12:25:10:35:10:7:6
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 1000
+-enable_ptx_file_line_stats 1
+
diff --git a/configs/QuadroFX5800/icnt_config_quadro_islip.txt b/configs/QuadroFX5800/icnt_config_quadro_islip.txt
new file mode 100644
index 0000000..be385a1
--- /dev/null
+++ b/configs/QuadroFX5800/icnt_config_quadro_islip.txt
@@ -0,0 +1,49 @@
+use_map = 0;
+flit_size = 32; 
+
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 18;
+n = 1;
+
+// Routing
+routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+// Flow control
+num_vcs     = 1; //4; 
+vc_buf_size = 8; //16;
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip;//i1_pim; //islip; //pim
+sw_allocator = islip;//i1_pim;//islip; //pim
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 0;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic (DO NOT CHANGE THIS)
+traffic = gpgpusim; 
+
+//not used in gpgpusim
+// const_flits_per_packet = 3;
+injection_process = gpgpu_injector;
+// Simulation 
+//not used in gpgpusim
+sim_type       = latency;
+injection_rate = 0.1;
+
+
+// Statistics for Interconnection (Added for GPGPU-Sim)
+MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
+DISPLAY_LAT_DIST = 1; // distribution of packet latencies
+DISPLAY_HOP_DIST = 1; // distribution of hop counts
+DISPLAY_PAIR_LATENCY = 0;