4 files changed, 30 insertions, 6 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config
index 62dd078..a1d6517 100644
--- a/configs/GTX480/gpgpusim.config
+++ b/configs/GTX480/gpgpusim.config
@@ -85,8 +85,13 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 16
+-gpgpu_dram_return_queue_size 116
 
 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
 -gpgpu_n_mem_per_ctrlr 2
diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config
index 256610f..8a9cd5b 100644
--- a/configs/QuadroFX5600/gpgpusim.config
+++ b/configs/QuadroFX5600/gpgpusim.config
@@ -49,10 +49,17 @@
 -network_mode 1 
 -inter_config_file icnt_config_islip.txt 
 
-# dram model config
+# dram scheduler config
 -gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 337.5MHz = 71
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 16
+-gpgpu_dram_return_queue_size 55
+
+# dram model config
 -gpgpu_n_mem_per_ctrlr 2
 -gpgpu_dram_buswidth 4 
 -gpgpu_dram_burst_length 4
diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config
index 81a5f1f..0df4b64 100644
--- a/configs/QuadroFX5800/gpgpusim.config
+++ b/configs/QuadroFX5800/gpgpusim.config
@@ -45,10 +45,17 @@
 -network_mode 1 
 -inter_config_file config_quadro_islip.icnt
 
-# dram model config
+# dram scheduler config
 -gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (30 core cycles).  I.e. 
+#   Total buffer space required = 30 x 800MHz / 325MHz = 74
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 16
+-gpgpu_dram_return_queue_size 58
+
+# dram model config
 -gpgpu_n_mem_per_ctrlr 2
 -gpgpu_dram_buswidth 4 
 -gpgpu_dram_burst_length 4
diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config
index 3100cbc..70e3420 100644
--- a/configs/TeslaC2050/gpgpusim.config
+++ b/configs/TeslaC2050/gpgpusim.config
@@ -88,8 +88,13 @@
 
 # dram model config
 -gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 750MHz / 575MHz = 130
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 16
+-gpgpu_dram_return_queue_size 114  
 
 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
 -gpgpu_n_mem_per_ctrlr 2