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-rw-r--r--configs/GTX480/config_fermi_islip.icnt59
-rw-r--r--configs/QuadroFX5600/icnt_config_islip.icnt59
-rw-r--r--configs/QuadroFX5800/config_quadro_islip.icnt58
-rw-r--r--configs/TeslaC2050/config_fermi_islip.icnt59
4 files changed, 159 insertions, 76 deletions
diff --git a/configs/GTX480/config_fermi_islip.icnt b/configs/GTX480/config_fermi_islip.icnt
index 07a4b10..7820e4e 100644
--- a/configs/GTX480/config_fermi_islip.icnt
+++ b/configs/GTX480/config_fermi_islip.icnt
@@ -1,6 +1,8 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
use_map = 0;
flit_size = 32;
+// currently we do not use this, see subnets below
network_count = 2;
// Topology
@@ -9,41 +11,60 @@ k = 27;
n = 1;
// Routing
-routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+routing_function = dest_tag;
// Flow control
-num_vcs = 1; //4;
-vc_buf_size = 8; //16;
+
+num_vcs = 1;
+vc_buf_size = 8;
+
wait_for_tail_credit = 0;
// Router architecture
-vc_allocator = islip;//i1_pim; //islip; //pim
-sw_allocator = islip;//i1_pim;//islip; //pim
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
alloc_iters = 1;
credit_delay = 0;
routing_delay = 0;
-vc_alloc_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
input_speedup = 2;
output_speedup = 1;
internal_speedup = 1.0;
-// Traffic (DO NOT CHANGE THIS)
-traffic = gpgpusim;
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
-//not used in gpgpusim
-// const_flits_per_packet = 3;
-injection_process = gpgpu_injector;
-// Simulation
-//not used in gpgpusim
-sim_type = latency;
+sim_type = gpgpusim;
+//sim_type = latency;
injection_rate = 0.1;
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
-// Statistics for Interconnection (Added for GPGPU-Sim)
-MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
-DISPLAY_LAT_DIST = 1; // distribution of packet latencies
-DISPLAY_HOP_DIST = 1; // distribution of hop counts
-DISPLAY_PAIR_LATENCY = 0;
diff --git a/configs/QuadroFX5600/icnt_config_islip.icnt b/configs/QuadroFX5600/icnt_config_islip.icnt
index b321d0a..de3bcc8 100644
--- a/configs/QuadroFX5600/icnt_config_islip.icnt
+++ b/configs/QuadroFX5600/icnt_config_islip.icnt
@@ -1,6 +1,8 @@
+//14*1 fly with 32 flits per packet under gpgpusim injection mode
use_map = 0;
flit_size = 32;
+// currently we donot use this, see subnets below
network_count = 2;
// Topology
@@ -9,41 +11,60 @@ k = 14;
n = 1;
// Routing
-routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+routing_function = dest_tag;
// Flow control
-num_vcs = 1; //4;
-vc_buf_size = 8; //16;
+
+num_vcs = 1;
+vc_buf_size = 8;
+
wait_for_tail_credit = 0;
// Router architecture
-vc_allocator = islip;//i1_pim; //islip; //pim
-sw_allocator = islip;//i1_pim;//islip; //pim
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
alloc_iters = 1;
credit_delay = 0;
routing_delay = 0;
-vc_alloc_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
input_speedup = 2;
output_speedup = 1;
internal_speedup = 1.0;
-// Traffic (DO NOT CHANGE THIS)
-traffic = gpgpusim;
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
-//not used in gpgpusim
-// const_flits_per_packet = 3;
-injection_process = gpgpu_injector;
-// Simulation
-//not used in gpgpusim
-sim_type = latency;
+sim_type = gpgpusim;
+//sim_type = latency;
injection_rate = 0.1;
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
-// Statistics for Interconnection (Added for GPGPU-Sim)
-MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
-DISPLAY_LAT_DIST = 1; // distribution of packet latencies
-DISPLAY_HOP_DIST = 1; // distribution of hop counts
-DISPLAY_PAIR_LATENCY = 0;
diff --git a/configs/QuadroFX5800/config_quadro_islip.icnt b/configs/QuadroFX5800/config_quadro_islip.icnt
index be385a1..cfe9cac 100644
--- a/configs/QuadroFX5800/config_quadro_islip.icnt
+++ b/configs/QuadroFX5800/config_quadro_islip.icnt
@@ -1,6 +1,8 @@
+//18*1 fly with 32 flits per packet under gpgpusim injection mode
use_map = 0;
flit_size = 32;
+// currently we donot use this, see subnets below
network_count = 2;
// Topology
@@ -9,41 +11,59 @@ k = 18;
n = 1;
// Routing
-routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+routing_function = dest_tag;
// Flow control
-num_vcs = 1; //4;
-vc_buf_size = 8; //16;
+
+num_vcs = 1;
+vc_buf_size = 8;
+
wait_for_tail_credit = 0;
// Router architecture
-vc_allocator = islip;//i1_pim; //islip; //pim
-sw_allocator = islip;//i1_pim;//islip; //pim
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
alloc_iters = 1;
credit_delay = 0;
routing_delay = 0;
-vc_alloc_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
input_speedup = 2;
output_speedup = 1;
internal_speedup = 1.0;
-// Traffic (DO NOT CHANGE THIS)
-traffic = gpgpusim;
+// Traffic, GPGPU-Sim does not use this
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
-//not used in gpgpusim
-// const_flits_per_packet = 3;
-injection_process = gpgpu_injector;
-// Simulation
-//not used in gpgpusim
-sim_type = latency;
+// Simulation - Don't change
+sim_type = gpgpusim;
+//sim_type = latency;
injection_rate = 0.1;
-// Statistics for Interconnection (Added for GPGPU-Sim)
-MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
-DISPLAY_LAT_DIST = 1; // distribution of packet latencies
-DISPLAY_HOP_DIST = 1; // distribution of hop counts
-DISPLAY_PAIR_LATENCY = 0;
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/TeslaC2050/config_fermi_islip.icnt b/configs/TeslaC2050/config_fermi_islip.icnt
index c1a272c..a11bd8e 100644
--- a/configs/TeslaC2050/config_fermi_islip.icnt
+++ b/configs/TeslaC2050/config_fermi_islip.icnt
@@ -1,6 +1,8 @@
+//20*1 fly with 32 flits per packet under gpgpusim injection mode
use_map = 0;
flit_size = 32;
+// currently we donot use this, see subnets below
network_count = 2;
// Topology
@@ -9,41 +11,60 @@ k = 26;
n = 1;
// Routing
-routing_function = dest_tag;//dim_order;//min_adapt;//dim_order;//_ni;
+
+routing_function = dest_tag;
// Flow control
-num_vcs = 1; //4;
-vc_buf_size = 8; //16;
+
+num_vcs = 1;
+vc_buf_size = 8;
+
wait_for_tail_credit = 0;
// Router architecture
-vc_allocator = islip;//i1_pim; //islip; //pim
-sw_allocator = islip;//i1_pim;//islip; //pim
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
alloc_iters = 1;
credit_delay = 0;
routing_delay = 0;
-vc_alloc_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
input_speedup = 2;
output_speedup = 1;
internal_speedup = 1.0;
-// Traffic (DO NOT CHANGE THIS)
-traffic = gpgpusim;
+// Traffic, GPGPU-Sim does not use this
+
+traffic = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
-//not used in gpgpusim
-// const_flits_per_packet = 3;
-injection_process = gpgpu_injector;
-// Simulation
-//not used in gpgpusim
-sim_type = latency;
+sim_type = gpgpusim;
+//sim_type = latency;
injection_rate = 0.1;
-// Statistics for Interconnection (Added for GPGPU-Sim)
-MATLAB_OUTPUT = 1; // output data in MATLAB friendly format
-DISPLAY_LAT_DIST = 1; // distribution of packet latencies
-DISPLAY_HOP_DIST = 1; // distribution of hop counts
-DISPLAY_PAIR_LATENCY = 0;
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 04:40:47 +0000