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-rw-r--r--configs/4.x-cfgs/SM6_TITANX/gpgpusim.config2
-rw-r--r--configs/4.x-cfgs/SM7_TITANV/gpgpusim.config2
2 files changed, 2 insertions, 2 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 3097d19..7368882 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -73,7 +73,7 @@
-gpgpu_n_cluster_ejection_buffer_size 32
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:128:4,16:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 32:32:32:32
-perf_sim_memcpy 0
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 8969168..da98547 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -78,7 +78,7 @@
-gpgpu_n_cluster_ejection_buffer_size 32
# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache
--gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32
+-gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:256:4,32:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 64:64:64:64
-perf_sim_memcpy 0