diff options
Diffstat (limited to 'cuda-kernels/log')
| -rw-r--r-- | cuda-kernels/log | 6328 |
1 files changed, 6328 insertions, 0 deletions
diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:80 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:80 => (ptx_parser.cc:144) init_directive_state + _1.ptx:81 => (ptx_parser.cc:672) add_option + _1.ptx:81 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:81 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:81 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:81 => (ptx_parser.cc:883) add_literal_int + _1.ptx:81 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:81 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:81 => (ptx_parser.cc:144) init_directive_state + _1.ptx:82 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:82 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:82 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:82 => (ptx_parser.cc:144) init_directive_state + _1.ptx:83 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:83 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:677) add_option + _1.ptx:83 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:83 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:83 => (ptx_parser.cc:929) add_address_operand + _1.ptx:83 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:83 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:83 => (ptx_parser.cc:295) add_instruction: mma_load + _1.ptx:83 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:83 => (ptx_parser.cc:144) init_directive_state + _1.ptx:84 => (ptx_parser.cc:672) add_option + _1.ptx:84 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:84 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:84 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:84 => (ptx_parser.cc:883) add_literal_int + _1.ptx:84 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:84 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:84 => (ptx_parser.cc:144) init_directive_state + _1.ptx:85 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:85 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:85 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:85 => (ptx_parser.cc:144) init_directive_state + _1.ptx:86 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:86 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:677) add_option + _1.ptx:86 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:86 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:86 => (ptx_parser.cc:929) add_address_operand + _1.ptx:86 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:86 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:86 => (ptx_parser.cc:295) add_instruction: mma_load + _1.ptx:86 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:86 => (ptx_parser.cc:144) init_directive_state + _1.ptx:87 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:87 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:87 => (ptx_parser.cc:889) add_literal_float + _1.ptx:87 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:87 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:87 => (ptx_parser.cc:144) init_directive_state + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:677) add_option + _1.ptx:88 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:88 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:88 => (ptx_parser.cc:295) add_instruction: mma + _1.ptx:88 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:88 => (ptx_parser.cc:144) init_directive_state + _1.ptx:90 => (ptx_parser.cc:643) add_label + _1.ptx:90 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:90 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:90 => (ptx_parser.cc:144) init_directive_state + _1.ptx:91 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:91 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:91 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:91 => (ptx_parser.cc:883) add_literal_int + _1.ptx:91 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:91 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:91 => (ptx_parser.cc:144) init_directive_state + _1.ptx:92 => (ptx_parser.cc:672) add_option + _1.ptx:92 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:92 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:92 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:92 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:92 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:92 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:92 => (ptx_parser.cc:144) init_directive_state + _1.ptx:93 => (ptx_parser.cc:672) add_option + _1.ptx:93 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:93 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:93 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:93 => (ptx_parser.cc:144) init_directive_state + _1.ptx:94 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:94 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:94 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:94 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:94 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:94 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:94 => (ptx_parser.cc:144) init_directive_state + _1.ptx:95 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:95 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:95 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:95 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:95 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:95 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:95 => (ptx_parser.cc:144) init_directive_state + _1.ptx:96 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:96 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:96 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:96 => (ptx_parser.cc:144) init_directive_state + _1.ptx:97 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:97 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:97 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:97 => (ptx_parser.cc:883) add_literal_int + _1.ptx:97 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:97 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:97 => (ptx_parser.cc:144) init_directive_state + _1.ptx:98 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:98 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:98 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:98 => (ptx_parser.cc:144) init_directive_state + _1.ptx:99 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:99 => (ptx_parser.cc:597) add_ptr_spec "global_space" + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:677) add_option + _1.ptx:99 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:99 => (ptx_parser.cc:929) add_address_operand + _1.ptx:99 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:99 => (ptx_parser.cc:737) add_8vector_operand + _1.ptx:99 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:99 => (ptx_parser.cc:295) add_instruction: mma_store + _1.ptx:99 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:99 => (ptx_parser.cc:144) init_directive_state + _1.ptx:101 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:101 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:101 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:101 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:101 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:101 => (ptx_parser.cc:144) init_directive_state + _1.ptx:103 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:103 => (ptx_parser.cc:295) add_instruction: sub + _1.ptx:103 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:103 => (ptx_parser.cc:144) init_directive_state + _1.ptx:104 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:104 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:104 => (ptx_parser.cc:929) add_address_operand + _1.ptx:104 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:104 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:104 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:104 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:104 => (ptx_parser.cc:144) init_directive_state + _1.ptx:105 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:105 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:105 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:105 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:105 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:105 => (ptx_parser.cc:144) init_directive_state + _1.ptx:106 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:106 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:106 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:106 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:106 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:106 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:106 => (ptx_parser.cc:144) init_directive_state + _1.ptx:108 => (ptx_parser.cc:208) start_instruction_group + _1.ptx:109 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:109 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:109 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:109 => (ptx_parser.cc:381) add_identifier "temp_param_reg" (111) + _1.ptx:109 => (ptx_parser.cc:319) add_variables + _1.ptx:109 => (ptx_parser.cc:144) init_directive_state + _1.ptx:109 => (ptx_parser.cc:219) add_directive + _1.ptx:109 => (ptx_parser.cc:144) init_directive_state + _1.ptx:111 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:111 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:111 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B64_TYPE + _1.ptx:111 => (ptx_parser.cc:381) add_identifier "param0" (112) +GPGPU-Sim PTX: allocating stack frame region for .param "param0" from 0x8 to 0x10 + _1.ptx:111 => (ptx_parser.cc:319) add_variables + _1.ptx:111 => (ptx_parser.cc:144) init_directive_state + _1.ptx:111 => (ptx_parser.cc:219) add_directive + _1.ptx:111 => (ptx_parser.cc:144) init_directive_state + _1.ptx:112 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:112 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:112 => (ptx_parser.cc:929) add_address_operand + _1.ptx:112 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:112 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:112 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:112 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:112 => (ptx_parser.cc:144) init_directive_state + _1.ptx:113 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:113 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:113 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B64_TYPE + _1.ptx:113 => (ptx_parser.cc:381) add_identifier "param1" (113) +GPGPU-Sim PTX: allocating stack frame region for .param "param1" from 0x10 to 0x18 + _1.ptx:113 => (ptx_parser.cc:319) add_variables + _1.ptx:113 => (ptx_parser.cc:144) init_directive_state + _1.ptx:113 => (ptx_parser.cc:219) add_directive + _1.ptx:113 => (ptx_parser.cc:144) init_directive_state + _1.ptx:114 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:114 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:114 => (ptx_parser.cc:929) add_address_operand + _1.ptx:114 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:114 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:114 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:114 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:114 => (ptx_parser.cc:144) init_directive_state + _1.ptx:115 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:115 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:115 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_unclassified scalar_type_spec=B32_TYPE + _1.ptx:115 => (ptx_parser.cc:381) add_identifier "retval0" (114) +GPGPU-Sim PTX: allocating stack frame region for .param "retval0" from 0x18 to 0x1c + _1.ptx:115 => (ptx_parser.cc:319) add_variables + _1.ptx:115 => (ptx_parser.cc:144) init_directive_state + _1.ptx:115 => (ptx_parser.cc:219) add_directive + _1.ptx:115 => (ptx_parser.cc:144) init_directive_state + _1.ptx:116 => (ptx_parser.cc:672) add_option + _1.ptx:116 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:117 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:119 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:121 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:121 => (ptx_parser.cc:295) add_instruction: call + _1.ptx:121 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:121 => (ptx_parser.cc:144) init_directive_state + _1.ptx:122 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:122 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:122 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:122 => (ptx_parser.cc:929) add_address_operand + _1.ptx:122 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:122 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:122 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:122 => (ptx_parser.cc:144) init_directive_state + _1.ptx:125 => (ptx_parser.cc:213) end_instruction_group + _1.ptx:126 => (ptx_parser.cc:295) add_instruction: ret + _1.ptx:126 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:126 => (ptx_parser.cc:144) init_directive_state + _1.ptx:127 => (ptx_parser.cc:227) end_function + _1.ptx:127 => (ptx_parser.cc:144) init_directive_state + _1.ptx:127 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:127 => (ptx_parser.cc:144) init_directive_state +GPGPU-Sim PTX: instruction assembly for function '_Z12wmma_exampleP6__halfS0_Pfiiiff'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding dominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding postdominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z12wmma_exampleP6__halfS0_Pfiiiff'... +GPGPU-Sim PTX: reconvergence points for _Z12wmma_exampleP6__halfS0_Pfiiiff... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x110 (_1.ptx:77) @!%p5 bra BB0_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x160 (_1.ptx:91) add.u64 %rd8, %SP, 0; +GPGPU-Sim PTX: 2 (potential) branch divergence @ PC=0x118 (_1.ptx:78) bra.uni BB0_1; +GPGPU-Sim PTX: immediate post dominator @ PC=0x120 (_1.ptx:81) mul.wide.s32 %rd4, %r2, 2; +GPGPU-Sim PTX: ... end of reconvergence points for _Z12wmma_exampleP6__halfS0_Pfiiiff +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z12wmma_exampleP6__halfS0_Pfiiiff'. + _1.ptx:127 => (ptx_parser.cc:237) function _Z12wmma_exampleP6__halfS0_Pfiiiff, PC = 0 + + _1.ptx:130 => (ptx_parser.cc:175) start_function + _1.ptx:130 => (ptx_parser.cc:144) init_directive_state + _1.ptx:130 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:130 => (ptx_parser.cc:144) init_directive_state + _1.ptx:130 => (ptx_parser.cc:189) add_function_name _Z17convertFp32ToFp16P6__halfPfi (entrypoint) + _1.ptx:131 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:131 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:131 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:131 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_0" (115) + _1.ptx:131 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_0" + _1.ptx:131 => (ptx_parser.cc:219) add_directive + _1.ptx:131 => (ptx_parser.cc:144) init_directive_state + _1.ptx:132 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:132 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:132 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:132 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_1" (116) + _1.ptx:132 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_1" + _1.ptx:132 => (ptx_parser.cc:219) add_directive + _1.ptx:132 => (ptx_parser.cc:144) init_directive_state + _1.ptx:133 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:133 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:133 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:134 => (ptx_parser.cc:381) add_identifier "_Z17convertFp32ToFp16P6__halfPfi_param_2" (117) + _1.ptx:134 => (ptx_parser.cc:577) add_function_arg "_Z17convertFp32ToFp16P6__halfPfi_param_2" + _1.ptx:134 => (ptx_parser.cc:219) add_directive + _1.ptx:134 => (ptx_parser.cc:144) init_directive_state + _1.ptx:136 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:136 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:136 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:136 => (ptx_parser.cc:381) add_identifier "%p0" (118) + _1.ptx:136 => (ptx_parser.cc:381) add_identifier "%p1" (119) + _1.ptx:136 => (ptx_parser.cc:319) add_variables + _1.ptx:136 => (ptx_parser.cc:144) init_directive_state + _1.ptx:136 => (ptx_parser.cc:219) add_directive + _1.ptx:136 => (ptx_parser.cc:144) init_directive_state + _1.ptx:137 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:137 => (ptx_parser.cc:631) add_scalar_type_spec "B16_TYPE" + _1.ptx:137 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B16_TYPE + _1.ptx:137 => (ptx_parser.cc:381) add_identifier "%rs0" (120) + _1.ptx:137 => (ptx_parser.cc:381) add_identifier "%rs1" (121) + _1.ptx:137 => (ptx_parser.cc:319) add_variables + _1.ptx:137 => (ptx_parser.cc:144) init_directive_state + _1.ptx:137 => (ptx_parser.cc:219) add_directive + _1.ptx:137 => (ptx_parser.cc:144) init_directive_state + _1.ptx:138 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:138 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:138 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:138 => (ptx_parser.cc:381) add_identifier "%f0" (122) + _1.ptx:138 => (ptx_parser.cc:381) add_identifier "%f1" (123) + _1.ptx:138 => (ptx_parser.cc:319) add_variables + _1.ptx:138 => (ptx_parser.cc:144) init_directive_state + _1.ptx:138 => (ptx_parser.cc:219) add_directive + _1.ptx:138 => (ptx_parser.cc:144) init_directive_state + _1.ptx:139 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:139 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:139 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r0" (124) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r1" (125) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r2" (126) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r3" (127) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r4" (128) + _1.ptx:139 => (ptx_parser.cc:381) add_identifier "%r5" (129) + _1.ptx:139 => (ptx_parser.cc:319) add_variables + _1.ptx:139 => (ptx_parser.cc:144) init_directive_state + _1.ptx:139 => (ptx_parser.cc:219) add_directive + _1.ptx:139 => (ptx_parser.cc:144) init_directive_state + _1.ptx:140 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:140 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:140 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd0" (130) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd1" (131) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd2" (132) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd3" (133) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd4" (134) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd5" (135) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd6" (136) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd7" (137) + _1.ptx:140 => (ptx_parser.cc:381) add_identifier "%rd8" (138) + _1.ptx:140 => (ptx_parser.cc:319) add_variables + _1.ptx:140 => (ptx_parser.cc:144) init_directive_state + _1.ptx:140 => (ptx_parser.cc:219) add_directive + _1.ptx:140 => (ptx_parser.cc:144) init_directive_state + _1.ptx:143 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:143 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:143 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:143 => (ptx_parser.cc:929) add_address_operand + _1.ptx:143 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:143 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:143 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:143 => (ptx_parser.cc:144) init_directive_state + _1.ptx:144 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:144 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:144 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:144 => (ptx_parser.cc:929) add_address_operand + _1.ptx:144 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:144 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:144 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:144 => (ptx_parser.cc:144) init_directive_state + _1.ptx:145 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:145 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:145 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:145 => (ptx_parser.cc:929) add_address_operand + _1.ptx:145 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:145 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:145 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:145 => (ptx_parser.cc:144) init_directive_state + _1.ptx:146 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:146 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:146 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:146 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:146 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:146 => (ptx_parser.cc:144) init_directive_state + _1.ptx:147 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:147 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:147 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:147 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:147 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:147 => (ptx_parser.cc:144) init_directive_state + _1.ptx:148 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:148 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:148 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:148 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:148 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:148 => (ptx_parser.cc:144) init_directive_state + _1.ptx:149 => (ptx_parser.cc:672) add_option + _1.ptx:149 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:149 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:149 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:149 => (ptx_parser.cc:144) init_directive_state + _1.ptx:150 => (ptx_parser.cc:672) add_option + _1.ptx:150 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:150 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:150 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:150 => (ptx_parser.cc:144) init_directive_state + _1.ptx:151 => (ptx_parser.cc:659) add_pred + _1.ptx:151 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:151 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:151 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:151 => (ptx_parser.cc:144) init_directive_state + _1.ptx:153 => (ptx_parser.cc:672) add_option + _1.ptx:153 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:153 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:153 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:153 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:153 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:153 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:153 => (ptx_parser.cc:144) init_directive_state + _1.ptx:154 => (ptx_parser.cc:672) add_option + _1.ptx:154 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:154 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:154 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:154 => (ptx_parser.cc:883) add_literal_int + _1.ptx:154 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:154 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:154 => (ptx_parser.cc:144) init_directive_state + _1.ptx:155 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:155 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:155 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:155 => (ptx_parser.cc:144) init_directive_state + _1.ptx:156 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:156 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:156 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:156 => (ptx_parser.cc:929) add_address_operand + _1.ptx:156 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:156 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:156 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:156 => (ptx_parser.cc:144) init_directive_state + _1.ptx:158 => (ptx_parser.cc:208) start_instruction_group + _1.ptx:158 => (ptx_parser.cc:672) add_option + _1.ptx:158 => (ptx_parser.cc:631) add_scalar_type_spec "F16_TYPE" + _1.ptx:158 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:158 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:158 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:158 => (ptx_parser.cc:295) add_instruction: cvt + _1.ptx:158 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:158 => (ptx_parser.cc:144) init_directive_state + _1.ptx:158 => (ptx_parser.cc:213) end_instruction_group + _1.ptx:161 => (ptx_parser.cc:672) add_option + _1.ptx:161 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:161 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:161 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:161 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:161 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:161 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:161 => (ptx_parser.cc:144) init_directive_state + _1.ptx:162 => (ptx_parser.cc:672) add_option + _1.ptx:162 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:162 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:162 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:162 => (ptx_parser.cc:883) add_literal_int + _1.ptx:162 => (ptx_parser.cc:295) add_instruction: mul + _1.ptx:162 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:162 => (ptx_parser.cc:144) init_directive_state + _1.ptx:163 => (ptx_parser.cc:631) add_scalar_type_spec "S64_TYPE" + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:163 => (ptx_parser.cc:295) add_instruction: add + _1.ptx:163 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:163 => (ptx_parser.cc:144) init_directive_state + _1.ptx:164 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:164 => (ptx_parser.cc:631) add_scalar_type_spec "U16_TYPE" + _1.ptx:164 => (ptx_parser.cc:929) add_address_operand + _1.ptx:164 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:164 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:164 => (ptx_parser.cc:295) add_instruction: st + _1.ptx:164 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:164 => (ptx_parser.cc:144) init_directive_state + _1.ptx:166 => (ptx_parser.cc:643) add_label + _1.ptx:166 => (ptx_parser.cc:295) add_instruction: <label> + _1.ptx:166 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:166 => (ptx_parser.cc:144) init_directive_state + _1.ptx:167 => (ptx_parser.cc:295) add_instruction: ret + _1.ptx:167 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:167 => (ptx_parser.cc:144) init_directive_state + _1.ptx:168 => (ptx_parser.cc:227) end_function + _1.ptx:168 => (ptx_parser.cc:144) init_directive_state + _1.ptx:168 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:168 => (ptx_parser.cc:144) init_directive_state +GPGPU-Sim PTX: instruction assembly for function '_Z17convertFp32ToFp16P6__halfPfi'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding dominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding postdominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z17convertFp32ToFp16P6__halfPfi'... +GPGPU-Sim PTX: reconvergence points for _Z17convertFp32ToFp16P6__halfPfi... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x238 (_1.ptx:151) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x288 (_1.ptx:167) ret; +GPGPU-Sim PTX: ... end of reconvergence points for _Z17convertFp32ToFp16P6__halfPfi +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z17convertFp32ToFp16P6__halfPfi'. + _1.ptx:168 => (ptx_parser.cc:237) function _Z17convertFp32ToFp16P6__halfPfi, PC = 504 + +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_VRbcDU" +Running: cat _ptx_VRbcDU | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_7Q1L71 +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_70 -v _ptx2_7Q1L71 --output-file /dev/null 2> _ptx_VRbcDUinfo" +GPGPU-Sim PTX: Kernel '_Z17convertFp32ToFp16P6__halfPfi' : regs=9, lmem=0, smem=0, cmem=372 +GPGPU-Sim PTX: Kernel '_Z12wmma_exampleP6__halfS0_Pfiiiff' : regs=32, lmem=0, smem=0, cmem=396 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_VRbcDU _ptx2_7Q1L71 _ptx_VRbcDUinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: initializing '$str' ... wrote 9 bytes +GPGPU-Sim PTX: finished loading globals (9 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z12wmma_exampleP6__halfS0_Pfiiiff : hostFun 0x0x401cf0, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403730, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c50, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ee0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404160, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404b60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x405060, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4052e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405500, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405940, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405b60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405d80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405fa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4061c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4063e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406600, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406820, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406a40, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406c60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406e80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4070a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4072c0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4074e0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951c0; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695200; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695240; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x695280; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x694580; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1992 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951a0; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6a0; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6c0; deviceAddress = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00002dac_00000000_12_cuda_device_runtime_compute_70_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951a8; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x40a6a4; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6951b0; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 +GPGPU-Sim PTX: cudaLaunch for 0x0x401dd7 (mode=performance simulation) on stream 0 + 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +GPGPU-Sim PTX: pushing kernel '_Z17convertFp32ToFp16P6__halfPfi' to stream 0, gridDim= (1,1,1) blockDim = (256,1,1) +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z17convertFp32ToFp16P6__halfPfi' +GPGPU-Sim uArch: CTA/core = 8, limited by: threads +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 256, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 0 (ipc= 0.0) sim_rate=0 (inst/sec) elapsed = 0:0:00:01 / Thu May 31 23:09:14 2018 +f2x: 0.000000 +f2x: 1.000000 +f2x: 2.000000 +f2x: 3.000000 +f2x: 4.000000 +f2x: 5.000000 +f2x: 6.000000 +f2x: 7.000000 +f2x: 8.000000 +f2x: 9.000000 +f2x: 10.000000 +f2x: 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data=5bf8 +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1146,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z17convertFp32ToFp16P6__halfPfi'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z17convertFp32ToFp16P6__halfPfi' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z17convertFp32ToFp16P6__halfPfi +kernel_launch_uid = 1 +gpu_sim_cycle = 1147 +gpu_sim_insn = 4608 +gpu_ipc = 4.0174 +gpu_tot_sim_cycle = 1147 +gpu_tot_sim_insn = 4608 +gpu_tot_ipc = 4.0174 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=4608 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 80 + L1I_total_cache_misses = 24 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 24 + L1C_total_cache_misses = 16 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 8 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 16 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 56 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 24 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 4864 +gpgpu_n_tot_w_icount = 152 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 8 +gpgpu_n_mem_write_global = 8 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 256 +gpgpu_n_store_insn = 256 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 768 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:9 W0_Idle:1630 W0_Scoreboard:613 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:152 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 64 {8:8,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 576 {72:8,} +traffic_breakdown_coretomem[INST_ACC_R] = 24 {8:3,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 1088 {136:8,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 64 {8:8,} +traffic_breakdown_memtocore[INST_ACC_R] = 408 {136:3,} +maxmrqlatency = 18 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 255 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 1146 +mrq_lat_table:16 0 4 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 5 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 24/15 = 1.600000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 8 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 252 254 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none none none none none none 0 +dram[6]: none none none none none none none none none none none none none none 0 0 +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 254 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2123 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003759 +n_activity=40 dram_eff=0.2 +bk0: 4a 2109i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2103i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=46 dram_eff=0.3478 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2109i bk11: 4a 2104i bk12: 0a 2127i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2123 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003759 +n_activity=40 dram_eff=0.2 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 4a 2109i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2118 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007519 +n_activity=80 dram_eff=0.2 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2129i bk14: 4a 2109i bk15: 4a 2108i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2128 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2128i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2128 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2128i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2128i bk6: 0a 2128i bk7: 0a 2128i bk8: 0a 2128i bk9: 0a 2128i bk10: 0a 2128i bk11: 0a 2128i bk12: 0a 2128i bk13: 0a 2128i bk14: 0a 2128i bk15: 0a 2128i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2110 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.01504 +n_activity=75 dram_eff=0.4267 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2067i bk11: 4a 2074i bk12: 0a 2126i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.037594 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2128 n_nop=2110 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.01504 +n_activity=73 dram_eff=0.4384 +bk0: 0a 2127i bk1: 0a 2128i bk2: 0a 2128i bk3: 0a 2128i bk4: 0a 2128i bk5: 0a 2129i bk6: 0a 2129i bk7: 0a 2129i bk8: 0a 2129i bk9: 0a 2129i bk10: 4a 2069i bk11: 4a 2073i bk12: 0a 2126i bk13: 0a 2127i bk14: 0a 2127i bk15: 0a 2127i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0390038 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 20 +L2_total_cache_misses = 16 +L2_total_cache_miss_rate = 0.8000 +L2_total_cache_pending_hits = 4 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 8 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 4 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 4 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.003 + +icnt_total_pkts_mem_to_simt=66 +icnt_total_pkts_simt_to_mem=36 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 8.5 + minimum = 6 + maximum = 20 +Network latency average = 8.5 + minimum = 6 + maximum = 20 +Slowest packet = 20 +Flit latency average = 7.78431 + minimum = 6 + maximum = 16 +Slowest flit = 54 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.000281484 + minimum = 0 (at node 0) + maximum = 0.008726 (at node 1) +Accepted packet rate average = 0.000281484 + minimum = 0 (at node 0) + maximum = 0.008726 (at node 1) +Injected flit rate average = 0.000717784 + minimum = 0 (at node 0) + maximum = 0.0157068 (at node 1) +Accepted flit rate average= 0.000717784 + minimum = 0 (at node 0) + maximum = 0.0287958 (at node 1) +Injected packet length average = 2.55 +Accepted packet length average = 2.55 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 4608 (inst/sec) +gpgpu_simulation_rate = 1147 (cycle/sec) + +GPGPU-Sim PTX: cudaLaunch for 0x0x401dd7 (mode=performance simulation) on stream 0 +GPGPU-Sim PTX: pushing kernel '_Z17convertFp32ToFp16P6__halfPfi' to stream 0, gridDim= (1,1,1) blockDim = (256,1,1) +GPGPU-Sim uArch: Shader 2 bind to kernel 2 '_Z17convertFp32ToFp16P6__halfPfi' +GPGPU-Sim uArch: core: 2, cta: 0, start_tid: 0, end_tid: 256, initialized @(1,1147) +f2x: 0.000000 +f2x: 1.000000 +f2x: 2.000000 +f2x: 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data=5bd8 +st:addr=3e20bf8 data=5be0 +st:addr=3e20bfa data=5be8 +st:addr=3e20bfc data=5bf0 +st:addr=3e20bfe data=5bf8 +GPGPU-Sim uArch: Shader 2 finished CTA #0 (909,1147), 0 CTAs running +GPGPU-Sim uArch: Shader 2 empty (last released kernel 2 '_Z17convertFp32ToFp16P6__halfPfi'). +GPGPU-Sim uArch: GPU detected kernel 2 '_Z17convertFp32ToFp16P6__halfPfi' finished on shader 2. +Destroy streams for kernel 2: size 0 +kernel_name = _Z17convertFp32ToFp16P6__halfPfi +kernel_launch_uid = 2 +gpu_sim_cycle = 910 +gpu_sim_insn = 4608 +gpu_ipc = 5.0637 +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 246 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 8.75 + minimum = 6 + maximum = 22 +Network latency average = 8.75 + minimum = 6 + maximum = 22 +Slowest packet = 60 +Flit latency average = 8.35294 + minimum = 6 + maximum = 18 +Slowest flit = 156 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.000354874 + minimum = 0 (at node 0) + maximum = 0.0110011 (at node 2) +Accepted packet rate average = 0.000354874 + minimum = 0 (at node 0) + maximum = 0.0110011 (at node 2) +Injected flit rate average = 0.000904929 + minimum = 0 (at node 0) + maximum = 0.019802 (at node 2) +Accepted flit rate average= 0.000904929 + minimum = 0 (at node 0) + maximum = 0.0363036 (at node 2) +Injected packet length average = 2.55 +Accepted packet length average = 2.55 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 9216 (inst/sec) +gpgpu_simulation_rate = 2057 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 +M = 16, N = 16, K = 16. alpha = 1.000000, beta = 1.000000 + +Running with wmma... + 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Network latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Flit latency average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Fragmentation average = -nan (6 samples) + minimum = nan (6 samples) + maximum = -nan (6 samples) +Injected packet rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Accepted packet rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Injected flit rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Accepted flit rate average = -nan (6 samples) + minimum = -nan (6 samples) + maximum = -nan (6 samples) +Injected packet size average = -nan (6 samples) +Accepted packet size average = -nan (6 samples) +Hops average = -nan (6 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 2057 +gpu_tot_sim_insn = 9216 +gpu_tot_ipc = 4.4803 +gpu_tot_issued_cta = 2 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=9216 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 160 + L1I_total_cache_misses = 48 + L1I_total_cache_miss_rate = 0.3000 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + +GPGPU-Sim PTX: cudaLaunch for 0x0x401cf0 (mode=performance simulation) on stream 0 + L1C_total_cache_accesses = 48 + L1C_total_cache_misses = 32 + L1C_total_cache_miss_rate = 0.6667 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 +GPGPU-Sim PTX: pushing kernel '_Z12wmma_exampleP6__halfS0_Pfiiiff' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 16 + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 32 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 112 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 48 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 9728 +gpgpu_n_tot_w_icount = 304 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 16 +gpgpu_n_mem_write_global = 16 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 2 +gpgpu_n_load_insn = 512 +gpgpu_n_store_insn = 512 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 1536 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:18 W0_Idle:2782 W0_Scoreboard:1230 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:304 +traffic_breakdown_coretomem[CONST_ACC_R] = 16 {8:2,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 128 {8:16,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 1152 {72:16,} +traffic_breakdown_coretomem[INST_ACC_R] = 48 {8:6,} +traffic_breakdown_memtocore[CONST_ACC_R] = 144 {72:2,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 2176 {136:16,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 128 {8:16,} +traffic_breakdown_memtocore[INST_ACC_R] = 816 {136:6,} +maxmrqlatency = 23 +maxdqlatency = 0 +maxmflatency = 265 +averagemflatency = 250 +max_icnt2mem_latency = 5 +max_icnt2sh_latency = 2056 +mrq_lat_table:29 0 5 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 19 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 7 11 0 0 0 0 0 0 15 1 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 850 859 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 806 808 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 812 813 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 815 817 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 820 822 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 567 568 0 0 0 228 +dram[6]: 0 0 0 0 0 0 0 0 0 0 571 574 0 0 488 1085 +dram[7]: 0 0 0 0 0 0 0 0 0 0 575 577 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 581 582 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1091 1098 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1105 1109 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 4.000000 4.000000 -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan 1.000000 +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan 1.000000 1.000000 +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 1.000000 -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 3.000000 3.000000 -nan -nan -nan -nan +average row locality = 44/25 = 1.760000 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 +dram[6]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 +dram[7]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 +total reads: 28 +min_bank_accesses = 0! +chip skew: 4/2 = 2.00 +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 +total reads: 16 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 384 none none none none none none none none none 164 172 none none none none +dram[1]: none none none none none none none none none none 185 191 none none none none +dram[2]: none none none none none none none none none none 254 255 none none none none +dram[3]: none none none none none none none none none none 256 257 none none none none +dram[4]: none none none none none none none none none none 257 258 none none none none +dram[5]: none none none none none none none none none none 252 255 none none none 0 +dram[6]: none none none none none none none none none none 255 256 none none 0 0 +dram[7]: none none none none none none none none none none 257 258 none none none none +dram[8]: none none none none none none none none none none 258 259 none none none none +dram[9]: none none none none none none none none none none 168 167 none none none none +dram[10]: none none none none none none none none none none 168 167 none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 253 265 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 252 263 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 254 255 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 256 257 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 252 255 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 255 256 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 257 258 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 258 259 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 265 261 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 265 262 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3793 n_act=3 n_pre=0 n_req=7 n_rd=12 n_write=8 bw_util=0.01048 +n_activity=126 dram_eff=0.3175 +bk0: 4a 3796i bk1: 0a 3815i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3817i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3775i bk11: 4a 3756i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0246331 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3790 n_act=2 n_pre=0 n_req=8 n_rd=16 n_write=8 bw_util=0.01258 +n_activity=125 dram_eff=0.384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 8a 3763i bk11: 8a 3736i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.019392 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3801 n_act=3 n_pre=0 n_req=3 n_rd=12 n_write=0 bw_util=0.006289 +n_activity=86 dram_eff=0.2791 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 4a 3796i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3796 n_act=4 n_pre=0 n_req=4 n_rd=16 n_write=0 bw_util=0.008386 +n_activity=126 dram_eff=0.254 +bk0: 0a 3814i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3816i bk14: 4a 3796i bk15: 4a 3795i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3792i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3806 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.004193 +n_activity=46 dram_eff=0.3478 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3797i bk11: 4a 3791i bk12: 0a 3815i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=75 dram_eff=0.4267 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3755i bk11: 4a 3762i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0209644 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=3816 n_nop=3798 n_act=2 n_pre=0 n_req=6 n_rd=8 n_write=8 bw_util=0.008386 +n_activity=73 dram_eff=0.4384 +bk0: 0a 3815i bk1: 0a 3816i bk2: 0a 3816i bk3: 0a 3816i bk4: 0a 3816i bk5: 0a 3817i bk6: 0a 3817i bk7: 0a 3817i bk8: 0a 3817i bk9: 0a 3817i bk10: 4a 3757i bk11: 4a 3761i bk12: 0a 3814i bk13: 0a 3815i bk14: 0a 3815i bk15: 0a 3815i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=3 avg=0.0217505 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 4, Miss = 2, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[1]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[2]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[3]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 3, Miss = 2, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[19]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[20]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_cache_bank[21]: Access = 2, Miss = 1, Miss_rate = 0.500, Pending_hits = 1, Reservation_fails = 0 +L2_total_cache_accesses = 40 +L2_total_cache_misses = 28 +L2_total_cache_miss_rate = 0.7000 +L2_total_cache_pending_hits = 8 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 16 + L2_cache_stats_breakdown[CONST_ACC_R][HIT] = 1 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 8 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 8 + L2_cache_stats_breakdown[INST_ACC_R][HIT] = 3 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 3 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.002 + +icnt_total_pkts_mem_to_simt=132 +icnt_total_pkts_simt_to_mem=72 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Network latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Flit latency average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Fragmentation average = -nan (7 samples) + minimum = nan (7 samples) + maximum = -nan (7 samples) +Injected packet rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Accepted packet rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Injected flit rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Accepted flit rate average = -nan (7 samples) + minimum = -nan (7 samples) + maximum = -nan (7 samples) +Injected packet size average = -nan (7 samples) +Accepted packet size average = -nan (7 samples) +Hops average = -nan (7 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 3 bind to kernel 3 '_Z12wmma_exampleP6__halfS0_Pfiiiff' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 3, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,2057) +mma_ld: thrd=0,addr=65144832, fp16(size=16), stride=16 +thread0=0,3c00,4000,4200,4400,4500,4600,4700 +mma_ld: thrd=1,addr=65144832, fp16(size=16), stride=16 +thread0=4800,4880,4900,4980,4a00,4a80,4b00,4b80 +mma_ld: thrd=2,addr=65144832, fp16(size=16), stride=16 +thread0=4c00,4c40,4c80,4cc0,4d00,4d40,4d80,4dc0 +mma_ld: thrd=3,addr=65144832, fp16(size=16), stride=16 +thread0=4e00,4e40,4e80,4ec0,4f00,4f40,4f80,4fc0 +mma_ld: thrd=4,addr=65144832, fp16(size=16), stride=16 +thread0=5000,5020,5040,5060,5080,50a0,50c0,50e0 +mma_ld: thrd=5,addr=65144832, fp16(size=16), stride=16 +thread0=5100,5120,5140,5160,5180,51a0,51c0,51e0 +mma_ld: thrd=6,addr=65144832, fp16(size=16), stride=16 +thread0=5200,5220,5240,5260,5280,52a0,52c0,52e0 +mma_ld: thrd=7,addr=65144832, fp16(size=16), stride=16 +thread0=5300,5320,5340,5360,5380,53a0,53c0,53e0 +mma_ld: thrd=8,addr=65144832, fp16(size=16), stride=16 +thread0=5400,5410,5420,5430,5440,5450,5460,5470 +mma_ld: thrd=9,addr=65144832, fp16(size=16), stride=16 +thread0=5480,5490,54a0,54b0,54c0,54d0,54e0,54f0 +mma_ld: thrd=10,addr=65144832, fp16(size=16), stride=16 +thread0=5500,5510,5520,5530,5540,5550,5560,5570 +mma_ld: thrd=11,addr=65144832, fp16(size=16), stride=16 +thread0=5580,5590,55a0,55b0,55c0,55d0,55e0,55f0 +mma_ld: thrd=12,addr=65144832, fp16(size=16), stride=16 +thread0=5600,5610,5620,5630,5640,5650,5660,5670 +mma_ld: thrd=13,addr=65144832, fp16(size=16), stride=16 +thread0=5680,5690,56a0,56b0,56c0,56d0,56e0,56f0 +mma_ld: thrd=14,addr=65144832, fp16(size=16), stride=16 +thread0=5700,5710,5720,5730,5740,5750,5760,5770 +mma_ld: thrd=15,addr=65144832, fp16(size=16), stride=16 +thread0=5780,5790,57a0,57b0,57c0,57d0,57e0,57f0 +mma_ld: thrd=16,addr=65144832, fp16(size=16), stride=16 +thread0=5800,5808,5810,5818,5820,5828,5830,5838 +mma_ld: thrd=17,addr=65144832, fp16(size=16), stride=16 +thread0=5840,5848,5850,5858,5860,5868,5870,5878 +mma_ld: thrd=18,addr=65144832, fp16(size=16), stride=16 +thread0=5880,5888,5890,5898,58a0,58a8,58b0,58b8 +mma_ld: thrd=19,addr=65144832, fp16(size=16), stride=16 +thread0=58c0,58c8,58d0,58d8,58e0,58e8,58f0,58f8 +mma_ld: thrd=20,addr=65144832, fp16(size=16), stride=16 +thread0=5900,5908,5910,5918,5920,5928,5930,5938 +mma_ld: thrd=21,addr=65144832, fp16(size=16), stride=16 +thread0=5940,5948,5950,5958,5960,5968,5970,5978 +mma_ld: thrd=22,addr=65144832, fp16(size=16), stride=16 +thread0=5980,5988,5990,5998,59a0,59a8,59b0,59b8 +mma_ld: thrd=23,addr=65144832, fp16(size=16), stride=16 +thread0=59c0,59c8,59d0,59d8,59e0,59e8,59f0,59f8 +mma_ld: thrd=24,addr=65144832, fp16(size=16), stride=16 +thread0=5a00,5a08,5a10,5a18,5a20,5a28,5a30,5a38 +mma_ld: thrd=25,addr=65144832, fp16(size=16), stride=16 +thread0=5a40,5a48,5a50,5a58,5a60,5a68,5a70,5a78 +mma_ld: thrd=26,addr=65144832, fp16(size=16), stride=16 +thread0=5a80,5a88,5a90,5a98,5aa0,5aa8,5ab0,5ab8 +mma_ld: thrd=27,addr=65144832, fp16(size=16), stride=16 +thread0=5ac0,5ac8,5ad0,5ad8,5ae0,5ae8,5af0,5af8 +mma_ld: thrd=28,addr=65144832, fp16(size=16), stride=16 +thread0=5b00,5b08,5b10,5b18,5b20,5b28,5b30,5b38 +mma_ld: thrd=29,addr=65144832, fp16(size=16), stride=16 +thread0=5b40,5b48,5b50,5b58,5b60,5b68,5b70,5b78 +mma_ld: thrd=30,addr=65144832, fp16(size=16), stride=16 +thread0=5b80,5b88,5b90,5b98,5ba0,5ba8,5bb0,5bb8 +mma_ld: thrd=31,addr=65144832, fp16(size=16), stride=16 +thread0=5bc0,5bc8,5bd0,5bd8,5be0,5be8,5bf0,5bf8 +mma_ld: thrd=0,addr=65145344, fp16(size=16), stride=16 +thread0=0,3c00,4000,4200,4400,4500,4600,4700 +mma_ld: thrd=1,addr=65145344, fp16(size=16), stride=16 +thread0=4800,4880,4900,4980,4a00,4a80,4b00,4b80 +mma_ld: thrd=2,addr=65145344, fp16(size=16), stride=16 +thread0=4c00,4c40,4c80,4cc0,4d00,4d40,4d80,4dc0 +mma_ld: thrd=3,addr=65145344, fp16(size=16), stride=16 +thread0=4e00,4e40,4e80,4ec0,4f00,4f40,4f80,4fc0 +mma_ld: thrd=4,addr=65145344, fp16(size=16), stride=16 +thread0=5000,5020,5040,5060,5080,50a0,50c0,50e0 +mma_ld: thrd=5,addr=65145344, fp16(size=16), stride=16 +thread0=5100,5120,5140,5160,5180,51a0,51c0,51e0 +mma_ld: thrd=6,addr=65145344, fp16(size=16), stride=16 +thread0=5200,5220,5240,5260,5280,52a0,52c0,52e0 +mma_ld: thrd=7,addr=65145344, fp16(size=16), stride=16 +thread0=5300,5320,5340,5360,5380,53a0,53c0,53e0 +mma_ld: thrd=8,addr=65145344, fp16(size=16), stride=16 +thread0=5400,5410,5420,5430,5440,5450,5460,5470 +mma_ld: thrd=9,addr=65145344, fp16(size=16), stride=16 +thread0=5480,5490,54a0,54b0,54c0,54d0,54e0,54f0 +mma_ld: thrd=10,addr=65145344, fp16(size=16), stride=16 +thread0=5500,5510,5520,5530,5540,5550,5560,5570 +mma_ld: thrd=11,addr=65145344, fp16(size=16), stride=16 +thread0=5580,5590,55a0,55b0,55c0,55d0,55e0,55f0 +mma_ld: thrd=12,addr=65145344, fp16(size=16), stride=16 +thread0=5600,5610,5620,5630,5640,5650,5660,5670 +mma_ld: thrd=13,addr=65145344, fp16(size=16), stride=16 +thread0=5680,5690,56a0,56b0,56c0,56d0,56e0,56f0 +mma_ld: thrd=14,addr=65145344, fp16(size=16), stride=16 +thread0=5700,5710,5720,5730,5740,5750,5760,5770 +mma_ld: thrd=15,addr=65145344, fp16(size=16), stride=16 +thread0=5780,5790,57a0,57b0,57c0,57d0,57e0,57f0 +mma_ld: thrd=16,addr=65145344, fp16(size=16), stride=16 +thread0=5800,5808,5810,5818,5820,5828,5830,5838 +mma_ld: thrd=17,addr=65145344, fp16(size=16), stride=16 +thread0=5840,5848,5850,5858,5860,5868,5870,5878 +mma_ld: thrd=18,addr=65145344, fp16(size=16), stride=16 +thread0=5880,5888,5890,5898,58a0,58a8,58b0,58b8 +mma_ld: thrd=19,addr=65145344, fp16(size=16), stride=16 +thread0=58c0,58c8,58d0,58d8,58e0,58e8,58f0,58f8 +mma_ld: thrd=20,addr=65145344, fp16(size=16), stride=16 +thread0=5900,5908,5910,5918,5920,5928,5930,5938 +mma_ld: thrd=21,addr=65145344, fp16(size=16), stride=16 +thread0=5940,5948,5950,5958,5960,5968,5970,5978 +mma_ld: thrd=22,addr=65145344, fp16(size=16), stride=16 +thread0=5980,5988,5990,5998,59a0,59a8,59b0,59b8 +mma_ld: thrd=23,addr=65145344, fp16(size=16), stride=16 +thread0=59c0,59c8,59d0,59d8,59e0,59e8,59f0,59f8 +mma_ld: thrd=24,addr=65145344, fp16(size=16), stride=16 +thread0=5a00,5a08,5a10,5a18,5a20,5a28,5a30,5a38 +mma_ld: thrd=25,addr=65145344, fp16(size=16), stride=16 +thread0=5a40,5a48,5a50,5a58,5a60,5a68,5a70,5a78 +mma_ld: thrd=26,addr=65145344, fp16(size=16), stride=16 +thread0=5a80,5a88,5a90,5a98,5aa0,5aa8,5ab0,5ab8 +mma_ld: thrd=27,addr=65145344, fp16(size=16), stride=16 +thread0=5ac0,5ac8,5ad0,5ad8,5ae0,5ae8,5af0,5af8 +mma_ld: thrd=28,addr=65145344, fp16(size=16), stride=16 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