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-rwxr-xr-xcuda-kernels/config_fermi_islip.icnt2
-rwxr-xr-xcuda-kernels/gpgpusim.config10
2 files changed, 6 insertions, 6 deletions
diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt
index a788090..3b8b496 100755
--- a/cuda-kernels/config_fermi_islip.icnt
+++ b/cuda-kernels/config_fermi_islip.icnt
@@ -7,7 +7,7 @@ network_count = 2;
// Topology
topology = fly;
-k = 62;
+k = 102;
n = 1;
// Routing
diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config
index 272ad3d..2510d21 100755
--- a/cuda-kernels/gpgpusim.config
+++ b/cuda-kernels/gpgpusim.config
@@ -10,7 +10,7 @@
-gpgpu_ptx_save_converted_ptxplus 0
# high level architecture configuration
--gpgpu_n_clusters 40
+-gpgpu_n_clusters 80
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 11
-gpgpu_n_sub_partition_per_mchannel 2
@@ -33,7 +33,7 @@
# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6
-gpgpu_num_sp_units 4
-gpgpu_num_sfu_units 1
# Instruction latencies and initiation intervals
@@ -72,15 +72,15 @@
-gpgpu_operand_collector_num_units_sp 20
-gpgpu_operand_collector_num_units_sfu 4
#-gpgpu_operand_collector_num_units_tensor_core 24
--gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_units_mem 8
-gpgpu_operand_collector_num_in_ports_sp 4
-gpgpu_operand_collector_num_out_ports_sp 4
-gpgpu_operand_collector_num_in_ports_sfu 1
-gpgpu_operand_collector_num_out_ports_sfu 1
#-gpgpu_operand_collector_num_in_ports_tensor_core 1
#-gpgpu_operand_collector_num_out_ports_tensor_core 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_operand_collector_num_in_ports_mem 10
+-gpgpu_operand_collector_num_out_ports_mem 10
# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
-gpgpu_num_reg_banks 32