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-rw-r--r--src/abstract_hardware_model.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 8d4d009..97b243e 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -632,6 +632,8 @@ enum divergence_support_t {
NUM_SIMD_MODEL
};
+const unsigned MAX_ACCESSES_PER_INSN_PER_THREAD = 8;
+
class warp_inst_t: public inst_t {
public:
// constructors
@@ -684,6 +686,7 @@ public:
m_per_scalar_thread.resize(m_config->warp_size);
m_per_scalar_thread_valid=true;
}
+ assert(num_addrs <= MAX_ACCESSES_PER_INSN_PER_THREAD);
for(unsigned i=0; i<num_addrs; i++)
m_per_scalar_thread[n].memreqaddr[i] = addr[i];
}
@@ -782,11 +785,11 @@ protected:
struct per_thread_info {
per_thread_info() {
- for(unsigned i=0; i<8; i++)
+ for(unsigned i=0; i<MAX_ACCESSES_PER_INSN_PER_THREAD; i++)
memreqaddr[i] = 0;
}
dram_callback_t callback;
- new_addr_type memreqaddr[8]; // effective address, upto 8 different requests (to support 32B access in 8 chunks of 4B each)
+ new_addr_type memreqaddr[MAX_ACCESSES_PER_INSN_PER_THREAD]; // effective address, upto 8 different requests (to support 32B access in 8 chunks of 4B each)
};
bool m_per_scalar_thread_valid;
std::vector<per_thread_info> m_per_scalar_thread;