1 files changed, 28 insertions, 49 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index b3e2965..7ff869c 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -53,17 +53,10 @@ typedef void * yyscan_t;
 #include "cuda_device_runtime.h"
 #include "../../libcuda/gpgpu_context.h"
 
-int gpgpu_ptx_instruction_classification;
-void ** g_inst_classification_stat = NULL;
-void ** g_inst_op_classification_stat= NULL;
 int g_debug_execution = 0;
-int g_debug_thread_uid = 0;
 addr_t g_debug_pc = 0xBEEF1518;
 // Output debug information to file options
 
-unsigned gpgpu_param_num_shaders = 0;
-
-unsigned cdp_latency[5];
 
 void cuda_sim::ptx_opcocde_latency_options (option_parser_t opp) {
 	option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
@@ -114,8 +107,6 @@ cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>"
 			"7200,8000,100,12000,1600");
 }
 
-static address_type get_converge_point(address_type pc);
-
 void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext)
 {
    std::string texname(name);
@@ -225,8 +216,6 @@ void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref)
    m_NameToTextureInfo.erase(texname);
 }
 
-unsigned g_assemble_code_next_pc=0; 
-std::map<unsigned,function_info*> g_pc_to_finfo;
 std::vector<ptx_instruction*> function_info::s_g_pc_to_insn;
 
 #define MAX_INST_SIZE 8 /*bytes*/
@@ -246,7 +235,7 @@ void function_info::ptx_assemble()
    fflush(stdout);
    std::list<ptx_instruction*>::iterator i;
 
-   addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions)
+   addr_t PC = gpgpu_ctx->func_sim->g_assemble_code_next_pc; // globally unique address (across functions)
    // start function on an aligned address
    for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) 
       s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
@@ -263,7 +252,7 @@ void function_info::ptx_assemble()
          const symbol *l = pI->get_label();
          labels[l->name()] = n;
       } else {
-         g_pc_to_finfo[PC] = this;
+         gpgpu_ctx->func_sim->g_pc_to_finfo[PC] = this;
          m_instr_mem[n] = pI;
          s_g_pc_to_insn.push_back(pI);
          assert(pI == s_g_pc_to_insn[PC]);
@@ -278,7 +267,7 @@ void function_info::ptx_assemble()
          PC += pI->inst_size();
       }
    }
-   g_assemble_code_next_pc=PC;
+   gpgpu_ctx->func_sim->g_assemble_code_next_pc=PC;
    for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions
       ptx_instruction *pI = m_instr_mem[ii];
       if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP  || pI->get_opcode() == CALLP_OP) {
@@ -503,7 +492,7 @@ void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count )
    }
 }
 
-void ptx_print_insn( address_type pc, FILE *fp )
+void cuda_sim::ptx_print_insn( address_type pc, FILE *fp )
 {
    std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
    if( f == g_pc_to_finfo.end() ) {
@@ -515,7 +504,7 @@ void ptx_print_insn( address_type pc, FILE *fp )
    finfo->print_insn(pc,fp);
 }
 
-std::string ptx_get_insn_str( address_type pc )
+std::string cuda_sim::ptx_get_insn_str( address_type pc )
 {
    std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
    if( f == g_pc_to_finfo.end() ) {
@@ -688,8 +677,11 @@ void ptx_instruction::set_opcode_and_latency()
 	sscanf(gpgpu_ctx->func_sim->opcode_initiation_tensor, "%u",
 			&tensor_init);
 	sscanf(gpgpu_ctx->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u",
-			&cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
-            &cdp_latency[3],&cdp_latency[4]);
+			&gpgpu_ctx->func_sim->cdp_latency[0],
+			&gpgpu_ctx->func_sim->cdp_latency[1],
+			&gpgpu_ctx->func_sim->cdp_latency[2],
+			&gpgpu_ctx->func_sim->cdp_latency[3],
+			&gpgpu_ctx->func_sim->cdp_latency[4]);
 
 	if(!m_operands.empty()){
 		std::vector<operand_info>::iterator it;
@@ -1098,7 +1090,7 @@ void ptx_instruction::pre_decode()
    }
 
    // get reconvergence pc
-   reconvergence_pc = get_converge_point(pc);
+   reconvergence_pc = gpgpu_ctx->func_sim->get_converge_point(pc);
 
    m_decoded=true;
 }
@@ -1462,7 +1454,7 @@ void function_info::ptx_jit_config(std::map<unsigned long long, size_t> mallocPt
 }
 
 template<int activate_level> 
-bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc)
+bool cuda_sim::ptx_debug_exec_dump_cond(int thd_uid, addr_t pc)
 {
    if (g_debug_execution >= activate_level) {
       // check each type of debug dump constraint to filter out dumps
@@ -1548,7 +1540,8 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
    }
    
    if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) {
-      if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) {
+      if ( (m_gpu->gpgpu_ctx->func_sim->g_debug_thread_uid==0)
+	      || (get_uid() == (unsigned)(m_gpu->gpgpu_ctx->func_sim->g_debug_thread_uid)) ) {
         
           clear_modifiedregs();
          enable_debug_trace();
@@ -1620,7 +1613,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
       fflush(m_gpu->get_ptx_inst_debug_file());
    }
 
-   if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) {
+   if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) {
       dim3 ctaid = get_ctaid();
       dim3 tid = get_tid();
       printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s)  [0x%llx]\n", 
@@ -1674,11 +1667,11 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
    }
 
    if ( g_debug_execution >= 6 ) {
-      if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) )
+      if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<6>(get_uid(), pc) )
          dump_modifiedregs(stdout);
    }
    if ( g_debug_execution >= 10 ) {
-      if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) )
+      if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<10>(get_uid(), pc) )
          dump_regs(stdout);
    }
    update_pc();
@@ -1688,7 +1681,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
    if(!(this->m_functionalSimulationMode))
        ptx_file_line_stats_add_exec_count(pI);
    
-   if ( gpgpu_ptx_instruction_classification ) {
+   if ( m_gpu->gpgpu_ctx->func_sim->gpgpu_ptx_instruction_classification ) {
       m_gpu->gpgpu_ctx->func_sim->init_inst_classification_stat();
       unsigned space_type=0;
       switch ( pI->get_space().get_type() ) {
@@ -1705,9 +1698,9 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
          space_type = 0 ;
          break;
       }
-      StatAddSample( g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count],  op_classification);
-      if (space_type) StatAddSample( g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], ( int )space_type);
-      StatAddSample( g_inst_op_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], (int)  pI->get_opcode() );
+      StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count],  op_classification);
+      if (space_type) StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], ( int )space_type);
+      StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_op_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], (int)  pI->get_opcode() );
    }
    if ( (m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn % 100000) == 0 ) {
       dim3 ctaid = get_ctaid();
@@ -1736,7 +1729,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
       
 }
 
-void set_param_gpgpu_num_shaders(int num_shaders)
+void cuda_sim::set_param_gpgpu_num_shaders(int num_shaders)
 {
    gpgpu_param_num_shaders = num_shaders;
 }
@@ -1818,7 +1811,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
    assert( max_cta_per_sm > 0 );
 
    //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid;
-   unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid;
+   unsigned sm_idx = hw_cta_id*gpu->gpgpu_ctx->func_sim->gpgpu_param_num_shaders + sid;
 
    if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) {
       if ( g_debug_execution >= 1 ) {
@@ -1948,9 +1941,6 @@ void print_splash()
    }
 }
 
-std::set<std::string>   g_globals;
-std::set<std::string>   g_constants;
-
 void cuda_sim::gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size )
 {
    printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size );
@@ -1963,7 +1953,7 @@ void cuda_sim::gpgpu_ptx_sim_register_global_variable(void *hostVar, const char
    g_global_name_lookup[hostVar] = deviceName;
 }
 
-void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu )
+void cuda_sim::gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu )
 {
    printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar);
    bool found_sym = false;
@@ -2033,13 +2023,9 @@ void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t co
    fflush(stdout);
 }
 
-int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle)
-
 extern int ptx_debug;
 
-bool g_cuda_launch_blocking = false;
-
-void read_sim_environment_variables() 
+void cuda_sim::read_sim_environment_variables()
 {
    ptx_debug = 0;
    g_debug_execution = 0;
@@ -2185,7 +2171,7 @@ void cuda_sim::gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL
            cta.execute(cp_count,temp);
 
             #if (CUDART_VERSION >= 5000)
-            	launch_all_device_kernels();
+               gpgpu_ctx->device_runtime->launch_all_device_kernels();
             #endif
          }
          else
@@ -2522,14 +2508,7 @@ void ptxinfo_opencl_addinfo( std::map<std::string,function_info*> &kernels )
    clear_ptxinfo();
 }
 
-struct rec_pts {
-   gpgpu_recon_t *s_kernel_recon_points;
-   int s_num_recon;
-};
-
-class std::map<function_info*,rec_pts> g_rpts;
-
-struct rec_pts find_reconvergence_points( function_info *finfo )
+struct rec_pts cuda_sim::find_reconvergence_points( function_info *finfo )
 {
    rec_pts tmp;
    std::map<function_info*,rec_pts>::iterator r=g_rpts.find(finfo);
@@ -2568,7 +2547,7 @@ address_type get_return_pc( void *thd )
     return the_thread->get_return_PC();
 }
 
-address_type get_converge_point( address_type pc ) 
+address_type cuda_sim::get_converge_point( address_type pc )
 {
    // the branch could encode the reconvergence point and/or a bit that indicates the 
    // reconvergence point is the return PC on the call stack in the case the branch has