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Diffstat (limited to 'src/cuda-sim/instructions.cc')
-rw-r--r--src/cuda-sim/instructions.cc85
1 files changed, 44 insertions, 41 deletions
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 11001d7..58a077e 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -31,6 +31,8 @@
#include "ptx_ir.h"
#include "opcodes.h"
#include "ptx_sim.h"
+typedef void * yyscan_t;
+class ptx_recognizer;
#include "ptx.tab.h"
#include <stdlib.h>
#include <math.h>
@@ -54,10 +56,10 @@
#include "cuda_device_runtime.h"
#include <stdarg.h>
+#include "../../libcuda/gpgpu_context.h"
+
using half_float::half;
-unsigned ptx_instruction::g_num_ptx_inst_uid=0;
-bool debug_tensorcore = 0;
const char *g_opcode_string[NUM_OPCODES] = {
@@ -1526,6 +1528,7 @@ void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread )
op2_data = thread->get_operand_value(op2, op2, PRED_TYPE, thread, 1);
op2_data.u32=!(op2_data.pred & 0x0001);
pI->set_bar_id(op1_data.u32);
+ pI->set_bar_count(thread->get_ntid().x * thread->get_ntid().y * thread->get_ntid().z);
switch(red_op){
case ATOMIC_POPC:
thread->popc_reduction(ctaid,op1_data.u32,op2_data.u32);
@@ -1836,14 +1839,14 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
for (thrd=0; thrd < core->get_warp_size(); thrd++){
thread = core->get_thread_info()[tid+thrd];
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("THREAD=%d\n:",thrd);
for(int operand_num=1;operand_num<=3;operand_num++){
const operand_info &src_a= pI->operand_lookup(operand_num);
unsigned nelem = src_a.get_vect_nelem();
ptx_reg_t v[8];
thread->get_vector_operand_values( src_a, v, nelem );
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("Thread%d_Iteration=%d\n:",thrd,operand_num);
for(k=0;k<nelem;k++){
printf("%x ",v[k].u64);
@@ -1865,14 +1868,14 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
if(!((operand_num==3)&&(type2==F32_TYPE))){
for(k=0;k<2*nelem;k++){
temp=nw_v[k].f16;
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("%.2f ",temp);
}
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("\n");
}
else{
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
for(k=0;k<8;k++){
printf("%.2f ",v[k].f32);
}
@@ -1883,7 +1886,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
case 1 ://operand 1
for(k=0;k<8;k++){
mapping(thrd,LOAD_A,a_layout,F16_TYPE,k,16,row,col,offset);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("A:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset);
matrix_a[row][col]=nw_v[offset];
}
@@ -1891,7 +1894,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
case 2 ://operand 2
for(k=0;k<8;k++){
mapping(thrd,LOAD_B,b_layout,F16_TYPE,k,16,row,col,offset);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("B:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset);
matrix_b[row][col]=nw_v[offset];
}
@@ -1899,7 +1902,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
case 3 ://operand 3
for(k=0;k<8;k++){
mapping(thrd,LOAD_C,ROW,type2,k,16,row,col,offset);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("C:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset);
if(type2!=F16_TYPE){
matrix_c[row][col]=v[offset];
@@ -1913,10 +1916,10 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
printf("Invalid Operand Index\n" );
}
}
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("\n");
}
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("MATRIX_A\n");
for (i=0;i<16;i++){
for(j=0;j<16;j++){
@@ -1976,7 +1979,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
}
}
}
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("MATRIX_D\n");
for (i=0;i<16;i++){
for(j=0;j<16;j++){
@@ -1995,7 +1998,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
int col_t[8];
for(k=0;k<8;k++){
mapping(thrd,LOAD_C,ROW,type,k,16,row_t[k],col_t[k],offset);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("mma:store:row:%d,col%d\n",row_t[k],col_t[k]);
}
thread = core->get_thread_info()[tid+thrd];
@@ -2004,7 +2007,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
if(type==F32_TYPE){
thread->set_wmma_vector_operand_values(dst,matrix_d[row_t[0]][col_t[0]],matrix_d[row_t[1]][col_t[1]],matrix_d[row_t[2]][col_t[2]],matrix_d[row_t[3]][col_t[3]],matrix_d[row_t[4]][col_t[4]],matrix_d[row_t[5]][col_t[5]],matrix_d[row_t[6]][col_t[6]],matrix_d[row_t[7]][col_t[7]]);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
{
printf("thread%d:",thrd);
for(k=0;k<8;k++){
@@ -2014,7 +2017,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
}
}
else if(type==F16_TYPE){
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("thread%d:",thrd);
for(k=0;k<8;k++){
temp=matrix_d[row_t[k]][col_t[k]].f16;
@@ -2034,7 +2037,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst )
nw_data3.s64=((matrix_d[row_t[4]][col_t[4]].s64 & 0xffff))|((matrix_d[row_t[5]][col_t[5]].s64&0xffff)<<16);
nw_data4.s64=((matrix_d[row_t[6]][col_t[6]].s64 & 0xffff))|((matrix_d[row_t[7]][col_t[7]].s64&0xffff)<<16);
thread->set_vector_operand_values(dst,nw_data1,nw_data2,nw_data3,nw_data4);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("thread%d=%x,%x,%x,%x",thrd,nw_data1.s64,nw_data2.s64,nw_data3.s64,nw_data4.s64);
}
@@ -2092,15 +2095,15 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread )
#if (CUDART_VERSION >= 5000)
//Jin: handle device runtime apis for CDP
else if(fname == "cudaGetParameterBufferV2") {
- gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func);
+ target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func);
return;
}
else if(fname == "cudaLaunchDeviceV2") {
- gpgpusim_cuda_launchDeviceV2(pI, thread, target_func);
+ target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_launchDeviceV2(pI, thread, target_func);
return;
}
else if(fname == "cudaStreamCreateWithFlags") {
- gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func);
+ target_func->gpgpu_ctx->device_runtime->gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func);
return;
}
#endif
@@ -2300,12 +2303,12 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign,
half_float::half tmp_h;
//assert( from_width == 32);
- enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero;
+ enum cudaRoundMode mode = cudaRoundZero;
switch (rounding_mode) {
- case RZI_OPTION: mode = cuda_math::cudaRoundZero; break;
- case RNI_OPTION: mode = cuda_math::cudaRoundNearest; break;
- case RMI_OPTION: mode = cuda_math::cudaRoundMinInf; break;
- case RPI_OPTION: mode = cuda_math::cudaRoundPosInf; break;
+ case RZI_OPTION: mode = cudaRoundZero; break;
+ case RNI_OPTION: mode = cudaRoundNearest; break;
+ case RMI_OPTION: mode = cudaRoundMinInf; break;
+ case RPI_OPTION: mode = cudaRoundPosInf; break;
default: break;
}
@@ -3128,7 +3131,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
decode_space(space,thread,src1,mem,addr);
type_info_key::type_decode(type,size,t);
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("mma_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32);
addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;
addr_t push_addr;
@@ -3148,7 +3151,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
mem->write(push_addr,size/8,&v[k].s64,thread,pI);
mem_txn_addr[num_mem_txn++]=push_addr;
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,v[0].s64,v[1].s64,v[2].s64,v[3].s64,v[4].s64,v[5].s64,v[6].s64,v[7].s64);
float temp;
int l;
@@ -3175,7 +3178,7 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
mem_txn_addr[num_mem_txn++]=push_addr;
}
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("wmma:store:thread%d=%x,%x,%x,%x,%x,%x,%x,%x\n",thrd,nw_v[0].s64,nw_v[1].s64,nw_v[2].s64,nw_v[3].s64,nw_v[4].s64,nw_v[5].s64,nw_v[6].s64,nw_v[7].s64);
}
}
@@ -3238,7 +3241,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
type_info_key::type_decode(type,size,t);
ptx_reg_t data[16];
- if(debug_tensorcore)
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore)
printf("mma_ld: thrd=%d,addr=%x, fpsize=%d, stride=%d\n",thrd,src1_data.u32,size,src2_data.u32);
addr_t new_addr = addr+thread_group_offset(thrd,wmma_type,wmma_layout,type,stride)*size/8;
@@ -3334,7 +3337,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
inst.data_size = 4; // 4 byte transaction
assert( inst.memory_op == insn_memory_op );
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
if(type==F16_TYPE){
printf("\nmma_ld:thread%d= ",thrd);
for(i=0;i<16;i++){
@@ -3384,7 +3387,7 @@ void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst )
thread->set_vector_operand_values(dst,nw_data[0],nw_data[1],nw_data[2],nw_data[3]);
else
thread->set_wmma_vector_operand_values(dst,nw_data[0],nw_data[1],nw_data[2],nw_data[3],nw_data[4],nw_data[5],nw_data[6],nw_data[7]);
- if(debug_tensorcore){
+ if(core->get_gpu()->gpgpu_ctx->debug_tensorcore){
printf("mma_ld:data[0].s64=%x,data[1].s64=%x,new_data[0].s64=%x\n",data[0].u64,data[1].u64,nw_data[0].u64);
printf("mma_ld:data[2].s64=%x,data[3].s64=%x,new_data[1].s64=%x\n",data[2].u64,data[3].u64,nw_data[1].u64);
printf("mma_ld:data[4].s64=%x,data[5].s64=%x,new_data[2].s64=%x\n",data[4].u64,data[5].u64,nw_data[2].u64);
@@ -5141,7 +5144,6 @@ void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not
void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
-ptx_reg_t* ptx_tex_regs = NULL;
union intfloat {
int a;
@@ -5255,9 +5257,10 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
unsigned c_type = pI->get_type2();
fflush(stdout);
ptx_reg_t data1, data2, data3, data4;
- if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4];
+ if (!thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs)
+ thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs = new ptx_reg_t[4];
unsigned nelem = src2.get_vect_nelem();
- thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture
+ thread->get_vector_operand_values(src2, thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture
/*
For programs with many streams, textures can be bound and unbound
asynchronously. This means we need to use the kernel's "snapshot" of
@@ -5294,7 +5297,7 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
height = cuArray->height;
if (texref->normalized) {
assert(c_type == F32_TYPE);
- x_f32 = ptx_tex_regs[0].f32;
+ x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
if (texref->addressMode[0] == cudaAddressModeClamp) {
x_f32 = (x_f32 > 1.0)? 1.0 : x_f32;
x_f32 = (x_f32 < 0.0)? 0.0 : x_f32;
@@ -5317,11 +5320,11 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
} else {
switch ( c_type ) {
case S32_TYPE:
- x = ptx_tex_regs[0].s32;
+ x = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].s32;
assert(texref->filterMode == cudaFilterModePoint);
break;
case F32_TYPE:
- x_f32 = ptx_tex_regs[0].f32;
+ x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling)
x = (int) x_f32;
break;
@@ -5344,8 +5347,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
width = cuArray->width;
height = cuArray->height;
if (texref->normalized) {
- x_f32 = reduce_precision(ptx_tex_regs[0].f32,16);
- y_f32 = reduce_precision(ptx_tex_regs[1].f32,15);
+ x_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32,16);
+ y_f32 = reduce_precision(thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32,15);
if (texref->addressMode[0]) {//clamp
if (x_f32<0) x_f32 = 0;
@@ -5375,8 +5378,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
y = (int) floor(y_f32 * height);
}
} else {
- x_f32 = ptx_tex_regs[0].f32;
- y_f32 = ptx_tex_regs[1].f32;
+ x_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[0].f32;
+ y_f32 = thread->get_gpu()->gpgpu_ctx->func_sim->ptx_tex_regs[1].f32;
alpha = x_f32 - floor(x_f32);
beta = y_f32 - floor(y_f32);
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 22:28:35 +0000