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-rw-r--r--src/cuda-sim/ptx-stats.cc32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc
index 8661a29..3e96984 100644
--- a/src/cuda-sim/ptx-stats.cc
+++ b/src/cuda-sim/ptx-stats.cc
@@ -168,10 +168,10 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn) {
void ptx_stats::ptx_file_line_stats_add_latency(unsigned pc, unsigned latency) {
const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
- if(pInsn != NULL)
- ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(),
- pInsn->source_line())]
- .latency += latency;
+ if (pInsn != NULL)
+ ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(),
+ pInsn->source_line())]
+ .latency += latency;
}
// attribute dram traffic to this ptx instruction (specified by the pc)
@@ -180,10 +180,10 @@ void ptx_stats::ptx_file_line_stats_add_dram_traffic(unsigned pc,
unsigned dram_traffic) {
const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
- if(pInsn != NULL)
- ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(),
- pInsn->source_line())]
- .dram_traffic += dram_traffic;
+ if (pInsn != NULL)
+ ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(),
+ pInsn->source_line())]
+ .dram_traffic += dram_traffic;
}
// attribute the number of shared memory access cycles to a ptx instruction
@@ -193,12 +193,12 @@ void ptx_stats::ptx_file_line_stats_add_smem_bank_conflict(
unsigned pc, unsigned n_way_bkconflict) {
const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
- if(pInsn != NULL) {
- ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line(
- pInsn->source_file(), pInsn->source_line())];
+ if (pInsn != NULL) {
+ ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line(
+ pInsn->source_file(), pInsn->source_line())];
line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict;
line_stats.smem_warp_count += 1;
- }
+ }
}
// attribute a non-coalesced mem access to a ptx instruction
@@ -208,12 +208,12 @@ void ptx_stats::ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc,
unsigned n_access) {
const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc);
- if(pInsn != NULL) {
- ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line(
- pInsn->source_file(), pInsn->source_line())];
+ if (pInsn != NULL) {
+ ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line(
+ pInsn->source_file(), pInsn->source_line())];
line_stats.gmem_n_access_total += n_access;
line_stats.gmem_warp_count += 1;
- }
+ }
}
// a class that tracks the inflight memory instructions of a shader core