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-rw-r--r--src/cuda-sim/cuda-sim.cc45
-rw-r--r--src/cuda-sim/instructions.cc1
-rw-r--r--src/cuda-sim/ptx.y3
-rw-r--r--src/cuda-sim/ptx_ir.cc2
-rw-r--r--src/cuda-sim/ptx_ir.h7
-rw-r--r--src/cuda-sim/ptx_parser.cc4
-rw-r--r--src/cuda-sim/ptx_parser.h1
7 files changed, 52 insertions, 11 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 9f24c69..99e054d 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -62,8 +62,8 @@ addr_t g_debug_pc = 0xBEEF1518;
unsigned g_ptx_sim_num_insn = 0;
unsigned gpgpu_param_num_shaders = 0;
-char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp;
-char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp;
+char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu;
+char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu;
char *cdp_latency_str;
unsigned cdp_latency[5];
@@ -80,6 +80,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
"Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 8,8,8,8,335",
"8,8,8,8,335");
+ option_parser_register(opp, "-ptx_opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu,
+ "Opcode latencies for SFU instructions"
+ "Default 8",
+ "8");
option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
"Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,4,4,32",
@@ -92,6 +96,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
"Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 8,8,8,8,130",
"8,8,8,8,130");
+ option_parser_register(opp, "-ptx_opcode_initiation_sfu", OPT_CSTR, &opcode_initiation_sfu,
+ "Opcode initiation intervals for sfu instructions"
+ "Default 8",
+ "8");
option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str,
"CDP API latency <cudaStreamCreateWithFlags, \
cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, \
@@ -393,6 +401,10 @@ void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t coun
char *src_data = (char*)src;
for (unsigned n=0; n < count; n ++ )
m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL);
+
+ // Copy into the performance model.
+ extern gpgpu_sim* g_the_gpu;
+ g_the_gpu->perf_memcpy_to_gpu(dst_start_addr, count);
if(g_debug_execution >= 3) {
printf( " done.\n");
fflush(stdout);
@@ -408,6 +420,10 @@ void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count )
unsigned char *dst_data = (unsigned char*)dst;
for (unsigned n=0; n < count; n ++ )
m_global_mem->read(src_start_addr+n,1,dst_data+n);
+
+ // Copy into the performance model.
+ extern gpgpu_sim* g_the_gpu;
+ g_the_gpu->perf_memcpy_to_gpu(src_start_addr, count);
if(g_debug_execution >= 3) {
printf( " done.\n");
fflush(stdout);
@@ -589,9 +605,11 @@ void ptx_instruction::set_opcode_and_latency()
unsigned int_latency[5];
unsigned fp_latency[5];
unsigned dp_latency[5];
+ unsigned sfu_latency;
unsigned int_init[5];
unsigned fp_init[5];
unsigned dp_init[5];
+ unsigned sfu_init;
/*
* [0] ADD,SUB
* [1] MAX,Min
@@ -608,6 +626,8 @@ void ptx_instruction::set_opcode_and_latency()
sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
&dp_latency[0],&dp_latency[1],&dp_latency[2],
&dp_latency[3],&dp_latency[4]);
+ sscanf(opcode_latency_sfu, "%u",
+ &sfu_latency);
sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
&int_init[0],&int_init[1],&int_init[2],
&int_init[3],&int_init[4]);
@@ -617,8 +637,10 @@ void ptx_instruction::set_opcode_and_latency()
sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u",
&dp_init[0],&dp_init[1],&dp_init[2],
&dp_init[3],&dp_init[4]);
+ sscanf(opcode_initiation_sfu, "%u",
+ &sfu_init);
sscanf(cdp_latency_str, "%u,%u,%u,%u,%u",
- &cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
+ &cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
&cdp_latency[3],&cdp_latency[4]);
if(!m_operands.empty()){
@@ -678,6 +700,7 @@ void ptx_instruction::set_opcode_and_latency()
case FF64_TYPE:
latency = dp_latency[0];
initiation_interval = dp_init[0];
+ op = DP_OP;
break;
case B32_TYPE:
case U32_TYPE:
@@ -699,6 +722,7 @@ void ptx_instruction::set_opcode_and_latency()
case FF64_TYPE:
latency = dp_latency[1];
initiation_interval = dp_init[1];
+ op = DP_OP;
break;
case B32_TYPE:
case U32_TYPE:
@@ -715,13 +739,12 @@ void ptx_instruction::set_opcode_and_latency()
case F32_TYPE:
latency = fp_latency[2];
initiation_interval = fp_init[2];
- op = ALU_SFU_OP;
break;
case F64_TYPE:
case FF64_TYPE:
latency = dp_latency[2];
initiation_interval = dp_init[2];
- op = ALU_SFU_OP;
+ op = DP_OP;
break;
case B32_TYPE:
case U32_TYPE:
@@ -744,6 +767,7 @@ void ptx_instruction::set_opcode_and_latency()
case FF64_TYPE:
latency = dp_latency[3];
initiation_interval = dp_init[3];
+ op = DP_OP;
break;
case B32_TYPE:
case U32_TYPE:
@@ -779,13 +803,13 @@ void ptx_instruction::set_opcode_and_latency()
break;
case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP:
//Using double to approximate those
- latency = dp_latency[2];
- initiation_interval = dp_init[2];
+ latency = sfu_latency;
+ initiation_interval = sfu_init;
op = SFU_OP;
break;
case SHFL_OP:
latency = 32;
- initiation_interval = 15;
+ initiation_interval = 4;
break;
default:
break;
@@ -874,6 +898,7 @@ void ptx_instruction::pre_decode()
switch( m_cache_option ) {
case CA_OPTION: cache_op = CACHE_ALL; break;
+ case NC_OPTION: cache_op = CACHE_L1; break;
case CG_OPTION: cache_op = CACHE_GLOBAL; break;
case CS_OPTION: cache_op = CACHE_STREAMING; break;
case LU_OPTION: cache_op = CACHE_LAST_USE; break;
@@ -1135,13 +1160,13 @@ void function_info::finalize( memory_space *param_mem )
// copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over
//Jin: copy parameter using aligned rules
const size_t word_size = 4;
- param_address = (param_address + size - 1) / size * size; //aligned with size
+ //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct
for (size_t idx = 0; idx < size; idx += word_size) {
const char *pdata = reinterpret_cast<const char*>(param_value.pdata) + idx; // cast to char * for ptr arithmetic
param_mem->write(param_address + idx, word_size, pdata,NULL,NULL);
}
unsigned offset = p.get_offset();
- assert(offset == param_address);
+ //assert(offset == param_address);
param->set_address(param_address);
param_address += size;
}
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 71286c9..e3b8970 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -33,6 +33,7 @@
#include "ptx.tab.h"
#include <stdlib.h>
#include <math.h>
+#include <cmath>
#include <fenv.h>
#include "cuda-math.h"
#include "../abstract_hardware_model.h"
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 342c37d..2783fc2 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -227,7 +227,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement
block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2);
func_header_info_int(",", $4);
- func_header_info_int(",", $6); }
+ func_header_info_int(",", $6);
+ maxnt_id($2, $4, $6);}
| MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); }
| MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); }
;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 8ebdcf8..ba6d7ed 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio
} else {
*func_info = new function_info(entry_point);
(*func_info)->set_name(name);
+ (*func_info)->set_maxnt_id(0);
m_function_info_lookup[key] = *func_info;
}
@@ -1210,6 +1211,7 @@ ptx_instruction::ptx_instruction( int opcode,
case EXTP_OPTION:
break;
case NC_OPTION:
+ m_cache_option = last_ptx_inst_option;
break;
case UP_OPTION:
case DOWN_OPTION:
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 8750187..f4d3641 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1245,6 +1245,7 @@ public:
const struct gpgpu_ptx_sim_info* get_kernel_info () const
{
+ assert (m_kernel_info.maxthreads == maxnt_id);
return &m_kernel_info;
}
@@ -1252,6 +1253,8 @@ public:
m_kernel_info = info;
m_kernel_info.ptx_version = 10*get_ptx_version().ver();
m_kernel_info.sm_target = get_ptx_version().target();
+ // THIS DEPENDS ON ptxas being called after the PTX is parsed.
+ m_kernel_info.maxthreads = maxnt_id;
}
symbol_table *get_symtab()
{
@@ -1275,7 +1278,11 @@ public:
}
bool is_entry_point() const { return m_entry_point; }
+ void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;}
+ unsigned get_maxnt_id() { return maxnt_id;}
+
private:
+ unsigned maxnt_id;
unsigned m_uid;
unsigned m_local_mem_framesize;
bool m_entry_point;
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 49c8472..6dc1f40 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c)
g_global_symbol_table->set_sm_target(a,b,c);
}
+void maxnt_id(int x, int y, int z) {
+ g_func_info->set_maxnt_id(x * y * z);
+}
+
void func_header(const char* a) {} //intentional dummy function
void func_header_info(const char* a) {} //intentional dummy function
void func_header_info_int(const char* a, int b) {} //intentional dummy function
diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h
index 32f3903..13042e1 100644
--- a/src/cuda-sim/ptx_parser.h
+++ b/src/cuda-sim/ptx_parser.h
@@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type );
void change_operand_neg( );
void set_immediate_operand_type( );
void version_header(double a);
+void maxnt_id(int x, int y, int z);
//Jin: handle instructino group for cdp
void start_inst_group();
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 10:03:57 +0000