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-rw-r--r--src/cuda-sim/cuda-sim.cc102
-rw-r--r--src/cuda-sim/ptx_ir.cc3
-rw-r--r--src/cuda-sim/ptx_ir.h11
-rw-r--r--src/cuda-sim/ptx_parser.cc10
4 files changed, 64 insertions, 62 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 89e89e8..e61659c 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -438,61 +438,64 @@ void ptx_print_insn( address_type pc, FILE *fp )
finfo->print_insn(pc,fp);
}
-static void get_opcode_info( const ptx_instruction *pI, unsigned opcode, unsigned *cycles, op_type *op )
+void ptx_instruction::get_opcode_info()
{
- *op = ALU_OP;
- *cycles = 1;
- if ( opcode == LD_OP ) {
- *op = LOAD_OP;
- } else if ( opcode == ST_OP ) {
- *op = STORE_OP;
- } else if ( opcode == BRA_OP ) {
- *op = BRANCH_OP;
- } else if ( opcode == BREAKADDR_OP ) {
- *op = BRANCH_OP;
- } else if ( opcode == TEX_OP ) {
- *op = LOAD_OP;
- } else if ( opcode == ATOM_OP ) {
- *op = LOAD_OP; // timing model treats this like load for now
- } else if ( opcode == BAR_OP ) {
- *op = BARRIER_OP;
- } else if ( opcode == MEMBAR_OP )
- *op = MEMORY_BARRIER_OP;
-
- // Floating point instructions
- if( opcode == RCP_OP ) {
- *cycles = 2;
- *op = SFU_OP;
- } else if ( opcode == LG2_OP || opcode == RSQRT_OP ) {
- *cycles = 4;
- *op = SFU_OP;
- } else if( opcode == SQRT_OP || opcode == SIN_OP || opcode == COS_OP || opcode == EX2_OP ) {
- *cycles = 4;
- *op = SFU_OP;
- } else if( opcode == DIV_OP ) {
+ op = ALU_OP;
+ initiation_interval = latency = 1;
+ switch( m_opcode ) {
+ case LD_OP: op = LOAD_OP; break;
+ case ST_OP: op = STORE_OP; break;
+ case BRA_OP: op = BRANCH_OP; break;
+ case BREAKADDR_OP: op = BRANCH_OP; break;
+ case TEX_OP: op = LOAD_OP; break;
+ case ATOM_OP: op = LOAD_OP; break;
+ case BAR_OP: op = BARRIER_OP; break;
+ case MEMBAR_OP: op = MEMORY_BARRIER_OP; break;
+ case RCP_OP:
+ latency = 2;
+ initiation_interval = 2;
+ op = SFU_OP;
+ break;
+ case LG2_OP: case RSQRT_OP:
+ latency = 4;
+ initiation_interval = 4;
+ op = SFU_OP;
+ break;
+ case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP:
+ latency = 10;
+ initiation_interval = 4;
+ op = SFU_OP;
+ break;
+ case DIV_OP:
// Floating point only
- if( pI->get_type() == F32_TYPE || pI->get_type() == F64_TYPE ) {
- *cycles = 4;
- *op = SFU_OP;
+ if( get_type() == F32_TYPE || get_type() == F64_TYPE ) {
+ latency = 10;
+ initiation_interval = 4;
+ op = SFU_OP;
}
- }
- // Integer instructions
- if( opcode == MUL_OP ) {
- if( pI->get_type() == B32_TYPE || pI->get_type() == U32_TYPE || pI->get_type() == S32_TYPE ) {
+ break;
+ case MUL_OP:
+ if( get_type() == B32_TYPE || get_type() == U32_TYPE || get_type() == S32_TYPE ) {
// 32-bit integer instruction
- *cycles = 5;
- *op = SFU_OP;
+ latency = 24;
+ initiation_interval = 5;
+ op = SFU_OP;
}
- if( pI->get_type() == F32_TYPE || pI->get_type() == F64_TYPE )
- *op = ALU_SFU_OP;
- }
- if( opcode == MAD_OP ) {
- if( pI->get_type() == B32_TYPE || pI->get_type() == U32_TYPE || pI->get_type() == S32_TYPE ) {
+ if( get_type() == F32_TYPE || get_type() == F64_TYPE ) {
+ op = ALU_SFU_OP;
+ }
+ break;
+ case MAD_OP:
+ if( get_type() == B32_TYPE || get_type() == U32_TYPE || get_type() == S32_TYPE ) {
// 32-bit integer instruction
- *cycles = 6;
- *op = SFU_OP;
+ latency = 30;
+ initiation_interval = 6;
+ op = SFU_OP;
}
- }
+ break;
+ default:
+ break;
+ }
}
void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const
@@ -519,7 +522,6 @@ void ptx_instruction::pre_decode()
ar2 = 0;
bool has_dst = false ;
- int opcode = get_opcode(); //determine the opcode
switch ( get_opcode() ) {
#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break;
@@ -530,7 +532,7 @@ void ptx_instruction::pre_decode()
break;
}
- get_opcode_info(this,opcode,&cycles,&op);
+ get_opcode_info();
// Get register operands
int n=0,m=0;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 8172f80..8d7fa11 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -983,7 +983,7 @@ ptx_instruction::ptx_instruction( int opcode,
const char *file,
unsigned line,
const char *source,
- unsigned warp_size ) : warp_inst_t(warp_size)
+ const shader_core_config *config ) : warp_inst_t(config)
{
m_uid = ++g_num_ptx_inst_uid;
m_PC = 0;
@@ -1011,7 +1011,6 @@ ptx_instruction::ptx_instruction( int opcode,
m_geom_spec = 0;
m_vector_spec = 0;
m_atomic_spec = 0;
- m_warp_size = warp_size;
m_membar_level = 0;
m_inst_size = 8; // bytes
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 07f2e36..84ded76 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -801,7 +801,7 @@ public:
const char *file,
unsigned line,
const char *source,
- unsigned warp_size );
+ const shader_core_config *config );
void print_insn() const;
virtual void print_insn( FILE *fp ) const;
@@ -940,7 +940,6 @@ public:
enum vote_mode_t { vote_any, vote_all, vote_uni };
enum vote_mode_t vote_mode() const { return m_vote_mode; }
- unsigned warp_size() const { return m_warp_size; }
int membar_level() const { return m_membar_level; }
bool has_memory_read() const {
@@ -966,6 +965,7 @@ public:
}
private:
+ void get_opcode_info();
basic_block_t *m_basic_block;
unsigned m_uid;
@@ -973,7 +973,6 @@ private:
std::string m_source_file;
unsigned m_source_line;
std::string m_source;
- unsigned m_warp_size;
const symbol *m_pred;
bool m_neg_pred;
@@ -1176,8 +1175,10 @@ public:
static const ptx_instruction* pc_to_instruction(unsigned pc)
{
- assert(pc <= s_g_pc_to_insn.size());
- return s_g_pc_to_insn[pc];
+ if( pc < s_g_pc_to_insn.size() )
+ return s_g_pc_to_insn[pc];
+ else
+ return NULL;
}
unsigned local_mem_framesize() const
{
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 5a65481..c4486a2 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -68,10 +68,10 @@
extern "C" int ptx_error( const char *s );
extern int ptx_lineno;
-static unsigned g_warp_size;
-void set_ptx_warp_size(unsigned warp_size)
+static const struct shader_core_config *g_shader_core_config;
+void set_ptx_warp_size(const struct shader_core_config * warp_size)
{
- g_warp_size=warp_size;
+ g_shader_core_config=warp_size;
}
static bool g_debug_ir_generation=false;
@@ -292,7 +292,7 @@ const ptx_instruction *ptx_instruction_lookup( const char *filename, unsigned li
void add_instruction()
{
DPRINTF("add_instruction: %s", ((g_opcode>0)?g_opcode_string[g_opcode]:"<label>") );
- assert( g_warp_size != 0 );
+ assert( g_shader_core_config != 0 );
ptx_instruction *i = new ptx_instruction( g_opcode,
g_pred,
g_neg_pred,
@@ -306,7 +306,7 @@ void add_instruction()
g_filename,
ptx_lineno,
linebuf,
- g_warp_size );
+ g_shader_core_config );
g_instructions.push_back(i);
g_inst_lookup[g_filename][ptx_lineno] = i;
init_instruction_state();
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 05:31:01 +0000