diff options
Diffstat (limited to 'src/cuda-sim')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 34 | ||||
| -rw-r--r-- | src/cuda-sim/ptx.y | 18 |
2 files changed, 36 insertions, 16 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39e2b7e..75dd3c8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -57,11 +57,11 @@ int g_debug_execution = 0; // Output debug information to file options void cuda_sim::ptx_opcocde_latency_options(option_parser_t opp) { - option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, - &opcode_latency_int, - "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>" - "Default 1,1,19,25,145", - "1,1,19,25,145"); + option_parser_register( + opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, + "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>" + "Default 1,1,19,25,145,32", + "1,1,19,25,145,32"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating " @@ -86,9 +86,9 @@ void cuda_sim::ptx_opcocde_latency_options(option_parser_t opp) { "64"); option_parser_register( opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>" - "Default 1,1,4,4,32", - "1,1,4,4,32"); + "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>" + "Default 1,1,4,4,32,4", + "1,1,4,4,32,4"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision " @@ -682,12 +682,12 @@ void ptx_instruction::set_bar_type() { } void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; unsigned sfu_latency; unsigned tensor_latency; - unsigned int_init[5]; + unsigned int_init[6]; unsigned fp_init[5]; unsigned dp_init[5]; unsigned sfu_init; @@ -698,10 +698,11 @@ void ptx_instruction::set_opcode_and_latency() { * [2] MUL * [3] MAD * [4] DIV + * [5] SHFL */ - sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0], &int_latency[1], &int_latency[2], &int_latency[3], - &int_latency[4]); + &int_latency[4], &int_latency[5]); sscanf(gpgpu_ctx->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0], &fp_latency[1], &fp_latency[2], &fp_latency[3], &fp_latency[4]); @@ -710,8 +711,9 @@ void ptx_instruction::set_opcode_and_latency() { &dp_latency[4]); sscanf(gpgpu_ctx->func_sim->opcode_latency_sfu, "%u", &sfu_latency); sscanf(gpgpu_ctx->func_sim->opcode_latency_tensor, "%u", &tensor_latency); - sscanf(gpgpu_ctx->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u", - &int_init[0], &int_init[1], &int_init[2], &int_init[3], &int_init[4]); + sscanf(gpgpu_ctx->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u,%u", + &int_init[0], &int_init[1], &int_init[2], &int_init[3], &int_init[4], + &int_init[5]); sscanf(gpgpu_ctx->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0], &fp_init[1], &fp_init[2], &fp_init[3], &fp_init[4]); sscanf(gpgpu_ctx->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u", @@ -940,8 +942,8 @@ void ptx_instruction::set_opcode_and_latency() { op = TENSOR_CORE_OP; break; case SHFL_OP: - latency = 4; - initiation_interval = 4; + latency = int_latency[5]; + initiation_interval = int_init[5]; break; default: break; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index a01c3c6..b38f783 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -298,6 +298,7 @@ ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND statement_block: LEFT_BRACE statement_list RIGHT_BRACE statement_list: directive_statement { recognizer->add_directive(); } + | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); } | instruction_statement { recognizer->add_instruction(); } | statement_list directive_statement { recognizer->add_directive(); } | statement_list instruction_statement { recognizer->add_instruction(); } @@ -414,6 +415,23 @@ initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { recognizer->add_array_in literal_list: literal_operand | literal_list COMMA literal_operand; +// TODO: This is currently hardcoded to handle and ignore one specific case +// that all prototype statements follow in the PTX from Pytorch. As a +// workaround, this parses and ignores both the prototype declaration +// and calling of the prototype (which conveniently comes right after the +// declaration for all cases.) This should be changed to handle both +// declaring the prototype, and actually calling it. +prototype_block: prototype_decl prototype_call + +prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON + +prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON + | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON + +prototype_param: /* empty */ + | PARAM_DIRECTIVE B64_TYPE IDENTIFIER + | PARAM_DIRECTIVE B32_TYPE IDENTIFIER + instruction_statement: instruction SEMI_COLON | IDENTIFIER COLON { recognizer->add_label($1); } | pred_spec instruction SEMI_COLON; |